The friendly Operating System for the Internet of Things
cpu/kw2x/include/cpu_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  * Copyright (C) 2014 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
25 #ifndef CPU_CONF_H
26 #define CPU_CONF_H
27 
28 #include "cpu_conf_common.h"
29 
30 #ifdef CPU_MODEL_KW21D256
31 #include "vendor/MKW22D5.h"
32 #elif CPU_MODEL_KW21D512
33 #include "vendor/MKW22D5.h"
34 #elif CPU_MODEL_KW22D512
35 #include "vendor/MKW22D5.h"
36 #else
37 #error "undefined CPU_MODEL"
38 #endif
39 
40 #ifdef __cplusplus
41 extern "C"
42 {
43 #endif
44 
49 #define CPU_DEFAULT_IRQ_PRIO (1U)
50 #define CPU_IRQ_NUMOF (65U)
51 #define CPU_FLASH_BASE (0x00000000)
52 
58 #define PIN_MUX_FUNCTION_ANALOG 0
59 #define PIN_MUX_FUNCTION_GPIO 1
60 
65 #define PIN_INTERRUPT_RISING 0b1001
66 #define PIN_INTERRUPT_FALLING 0b1010
67 #define PIN_INTERRUPT_EDGE 0b1011
68 
72 #define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
73 #define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
74 #define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
75 #define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
76 #define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
77 
82 #define LPTIMER_CLKSRC LPTIMER_CLKSRC_LPO
83 #define LPTIMER_DEV (LPTMR0)
84 #define LPTIMER_CLKEN() (SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK)
85 #define LPTIMER_CLKDIS() (SIM->SCGC5 &= ~SIM_SCGC5_PTMR_MASK)
86 #define LPTIMER_CNR_NEEDS_LATCHING 1
93 #define KW2XDRF_PORT_DEV PORTB
94 #define KW2XDRF_PORT PORT_B
95 #define KW2XDRF_GPIO GPIOB
96 #define KW2XDRF_PORT_IRQn PORTB_IRQn
97 
98 #define KW2XDRF_PORT_CLKEN() (PORTB_CLOCK_GATE = 1)
99 #define KW2XDRF_PIN_AF 2
100 #define KW2XDRF_PCS0_PIN 10
101 #define KW2XDRF_SCK_PIN 11
102 #define KW2XDRF_SOUT_PIN 16
103 #define KW2XDRF_SIN_PIN 17
104 #define KW2XDRF_RST_PIN 19
105 #define KW2XDRF_IRQ_PIN 3
106 #define KW2XDRF_CLK_CTRL_PORT PORT_C
107 #define KW2XDRF_CLK_CTRL_PORT_DEV PORTC
108 #define KW2XDRF_CLK_CTRL_GPIO GPIOC
109 #define KW2XDRF_CLK_CTRL_CLKEN() (PORTC_CLOCK_GATE = 1)
110 #define KW2XDRF_CLK_CTRL_PIN 0
114 #ifdef __cplusplus
115 }
116 #endif
117 
118 #endif /* CPU_CONF_H */
119 
Common CPU definitione for Cortex-M family based MCUs.