The friendly Operating System for the Internet of Things
cpu/k64f/include/cpu_conf.h
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1 /*
2  * Copyright (C) 2015 Freie Universit├Ąt Berlin
3  * Copyright (C) 2015 PHYTEC Messtechnik GmbH
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser General
6  * Public License v2.1. See the file LICENSE in the top level directory for more
7  * details.
8  */
9 
24 #ifndef CPU_CONF_H
25 #define CPU_CONF_H
26 
27 #include "cpu_conf_common.h"
28 
29 #ifdef CPU_MODEL_MK64FN1M0VLL12
30 #include "vendor/MK64F12.h"
31 #else
32 #error "undefined CPU_MODEL"
33 #endif
34 
35 #ifdef __cplusplus
36 extern "C"
37 {
38 #endif
39 
44 #define CPU_DEFAULT_IRQ_PRIO (1U)
45 #define CPU_IRQ_NUMOF (86U)
46 #define CPU_FLASH_BASE (0x00000000)
47 
53 #define PIN_MUX_FUNCTION_ANALOG 0
54 #define PIN_MUX_FUNCTION_GPIO 1
55 
60 #define PIN_INTERRUPT_RISING 0b1001
61 #define PIN_INTERRUPT_FALLING 0b1010
62 #define PIN_INTERRUPT_EDGE 0b1011
63 
67 #define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
68 #define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
69 #define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
70 #define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
71 #define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
72 
77 #define LPTIMER_CLKSRC LPTIMER_CLKSRC_LPO
78 #define LPTIMER_DEV (LPTMR0)
79 #define LPTIMER_CLKEN() (SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK)
80 #define LPTIMER_CLKDIS() (SIM->SCGC5 &= ~SIM_SCGC5_PTMR_MASK)
81 #define LPTIMER_CNR_NEEDS_LATCHING 1
83 #ifdef __cplusplus
84 }
85 #endif
86 
87 #endif /* CPU_CONF_H */
88 
Common CPU definitione for Cortex-M family based MCUs.