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cpu/k60/include/cpu_conf.h
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1 /*
2  * Copyright (C) 2015 Eistec AB
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
21 #ifndef CPU_CONF_H
22 #define CPU_CONF_H
23 
24 #include "cpu_conf_common.h"
25 
26 #ifdef __cplusplus
27 extern "C"
28 {
29 #endif
30 
31 #include <stdint.h>
32 
33 #if defined(CPU_MODEL_K60DN512VLL10) || defined(CPU_MODEL_K60DN256VLL10)
34 
35 /* Rev. 2.x silicon */
36 #define K60_CPU_REV 2
37 #include "vendor/MK60D10.h"
38 
41 #define K60_EXPECTED_CPUID 0x410fc241u
42 
43 /* K60 rev 2.x replaced the RNG module in 1.x by the RNGA PRNG module */
44 #define KINETIS_RNGA (RNG)
45 
46 #elif defined(CPU_MODEL_K60DN512ZVLL10) || defined(CPU_MODEL_K60DN256ZVLL10)
47 
48 /* Rev. 1.x silicon */
49 #define K60_CPU_REV 1
50 #include "vendor/MK60DZ10.h"
51 
54 #define K60_EXPECTED_CPUID 0x410fc240u
55 
56 /* K60 rev 1.x has the cryptographically strong RNGB module */
57 #define KINETIS_RNGB (RNG)
58 
59 #else
60 #error Unknown CPU model. Update Makefile.include in the board directory.
61 #endif
62 
63 /* Compatibility definitions between the two different Freescale headers */
64 #include "MK60-comp.h"
65 
70 #define CPU_DEFAULT_IRQ_PRIO (1U)
71 #define CPU_IRQ_NUMOF (104U)
72 #define CPU_FLASH_BASE (0x00000000)
73 
79 #define PIN_MUX_FUNCTION_ANALOG 0
80 #define PIN_MUX_FUNCTION_GPIO 1
81 
86 #define PIN_INTERRUPT_RISING 0b1001
87 #define PIN_INTERRUPT_FALLING 0b1010
88 #define PIN_INTERRUPT_EDGE 0b1011
89 
93 #define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
94 #define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
95 #define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
96 #define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
97 #define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
98 
105 #define KINETIS_UART UART_Type
106 
112 #define LPTIMER_DEV (LPTMR0)
113 #define LPTIMER_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 1)
114 #define LPTIMER_CLKDIS() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 0)
115 #define LPTIMER_CLKSRC_MCGIRCLK 0
116 #define LPTIMER_CLKSRC_LPO 1
117 #define LPTIMER_CLKSRC_ERCLK32K 2
118 #define LPTIMER_CLKSRC_OSCERCLK 3
120 #ifndef LPTIMER_CLKSRC
121 #define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K
122 #endif
123 
124 #if (LPTIMER_CLKSRC == LPTIMER_CLKSRC_MCGIRCLK)
125 #define LPTIMER_CLK_PRESCALE 1
126 #define LPTIMER_SPEED 1000000
127 #elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_OSCERCLK)
128 #define LPTIMER_CLK_PRESCALE 1
129 #define LPTIMER_SPEED 1000000
130 #elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_ERCLK32K)
131 #define LPTIMER_CLK_PRESCALE 0
132 #define LPTIMER_SPEED 32768
133 #else
134 #define LPTIMER_CLK_PRESCALE 0
135 #define LPTIMER_SPEED 1000
136 #endif
137 
139 #define LPTIMER_IRQ_PRIO 1
140 
141 #define LPTIMER_IRQ_CHAN LPTMR0_IRQn
142 
143 #if K60_CPU_REV == 1
144 /*
145  * The CNR register latching in LPTMR0 was added in silicon rev 2.x. With
146  * rev 1.x we do not need to do anything in order to read the current timer counter
147  * value
148  */
149 #define LPTIMER_CNR_NEEDS_LATCHING 0
150 
151 #elif K60_CPU_REV == 2
152 
153 #define LPTIMER_CNR_NEEDS_LATCHING 1
154 
155 #endif
156 
162 #if K60_CPU_REV == 1
163 #define KINETIS_PMCTRL MC->PMCTRL
164 #define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = MC_PMCTRL_LPLLSM(x) | MC_PMCTRL_LPWUI_MASK)
165 /* Clear LLS protection, clear VLPS, VLPW, VLPR protection */
166 /* Note: This register can only be written once after each reset, so we must
167  * enable all power modes that we wish to use. */
168 #define KINETIS_UNLOCK_PMPROT() (MC->PMPROT |= MC_PMPROT_ALLS_MASK | MC_PMPROT_AVLP_MASK)
169 #elif K60_CPU_REV == 2
170 #define KINETIS_PMCTRL SMC->PMCTRL
171 #define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK)
172 #define KINETIS_PMPROT_UNLOCK() (SMC->PMPROT |= SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK)
173 #else
174 #error Unknown K60 CPU revision!
175 #endif
176 
182 #define KINETIS_POWER_MODE_NORMAL (0b000)
183 
184 #define KINETIS_POWER_MODE_VLPS (0b010)
185 
186 #define KINETIS_POWER_MODE_LLS (0b011)
187 
195 #define KINETIS_LLWU_WAKEUP_MODULE_LPTMR 0
196 
200 #define KINETIS_LLWU_IRQ LLW_IRQn
201 
205 #define LLWU_UNLOCK() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1)
206 
212 typedef enum llwu_wakeup_module {
213  KINETIS_LPM_WAKEUP_MODULE_LPTMR = 0,
214  KINETIS_LPM_WAKEUP_MODULE_CMP0 = 1,
215  KINETIS_LPM_WAKEUP_MODULE_CMP1 = 2,
216  KINETIS_LPM_WAKEUP_MODULE_CMP2 = 3,
217  KINETIS_LPM_WAKEUP_MODULE_TSI = 4,
218  KINETIS_LPM_WAKEUP_MODULE_RTC_ALARM = 5,
219  KINETIS_LPM_WAKEUP_MODULE_RESERVED = 6,
220  KINETIS_LPM_WAKEUP_MODULE_RTC_SECONDS = 7,
221  KINETIS_LPM_WAKEUP_MODULE_END,
223 
229 typedef enum llwu_wakeup_pin {
230  KINETIS_LPM_WAKEUP_PIN_PTE1 = 0,
231  KINETIS_LPM_WAKEUP_PIN_PTE2 = 1,
232  KINETIS_LPM_WAKEUP_PIN_PTE4 = 2,
233  KINETIS_LPM_WAKEUP_PIN_PTA4 = 3,
234  KINETIS_LPM_WAKEUP_PIN_PTA13 = 4,
235  KINETIS_LPM_WAKEUP_PIN_PTB0 = 5,
236  KINETIS_LPM_WAKEUP_PIN_PTC1 = 6,
237  KINETIS_LPM_WAKEUP_PIN_PTC3 = 7,
238  KINETIS_LPM_WAKEUP_PIN_PTC4 = 8,
239  KINETIS_LPM_WAKEUP_PIN_PTC5 = 9,
240  KINETIS_LPM_WAKEUP_PIN_PTC6 = 10,
241  KINETIS_LPM_WAKEUP_PIN_PTC11 = 11,
242  KINETIS_LPM_WAKEUP_PIN_PTD0 = 12,
243  KINETIS_LPM_WAKEUP_PIN_PTD2 = 13,
244  KINETIS_LPM_WAKEUP_PIN_PTD4 = 14,
245  KINETIS_LPM_WAKEUP_PIN_PTD6 = 15,
246  KINETIS_LPM_WAKEUP_PIN_END
248 
255 /* Generic bitband conversion routine */
263 #define BITBAND_ADDR(addr, bit) ((((uint32_t) (addr)) & 0xF0000000u) + 0x2000000 + ((((uint32_t) (addr)) & 0xFFFFF) << 5) + ((bit) << 2))
264 
271 #define BITBAND_VAR32(var, bit) (*((uint32_t volatile*) BITBAND_ADDR(&(var), (bit))))
272 
279 #define BITBAND_VAR16(var, bit) (*((uint16_t volatile*) BITBAND_ADDR(&(var), (bit))))
280 
287 #define BITBAND_VAR8(var, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(var), (bit))))
288 
290 #ifdef __cplusplus
291 }
292 #endif
293 
294 #endif /* CPU_CONF_H */
295 
enum llwu_wakeup_pin llwu_wakeup_pin_t
enum that maps physical pins to wakeup pin numbers in LLWU module
Common CPU definitione for Cortex-M family based MCUs.
Compatibility definitions between MK60D10.h and MK60DZ10.h.
llwu_wakeup_pin
enum that maps physical pins to wakeup pin numbers in LLWU module
llwu_wakeup_module
Internal modules whose interrupts are mapped to LLWU wake up sources.
enum llwu_wakeup_module llwu_wakeup_module_t
Internal modules whose interrupts are mapped to LLWU wake up sources.