cpu/k60/include/cpu_conf.h
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1 /*
2  * Copyright (C) 2015 Eistec AB
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
21 #ifndef CPU_CONF_H
22 #define CPU_CONF_H
23 
24 #include "cpu_conf_common.h"
25 
26 #ifdef __cplusplus
27 extern "C"
28 {
29 #endif
30 
31 #include <stdint.h>
32 
33 #if defined(CPU_MODEL_MK60DN512VLL10) || defined(CPU_MODEL_MK60DN256VLL10)
34 #include "vendor/MK60D10.h"
35 
38 #define K60_EXPECTED_CPUID 0x410fc241u
39 
40 /* K60 rev 2.x replaced the RNG module in 1.x by the RNGA PRNG module */
41 #define KINETIS_RNGA (RNG)
42 #else
43 #error Unknown CPU model. Update Makefile.include in the board directory.
44 #endif
45 
50 #define CPU_DEFAULT_IRQ_PRIO (1U)
51 #define CPU_IRQ_NUMOF (104U)
52 #define CPU_FLASH_BASE (0x00000000)
53 
59 #define PIN_MUX_FUNCTION_ANALOG 0
60 #define PIN_MUX_FUNCTION_GPIO 1
61 
66 #define PIN_INTERRUPT_RISING 0b1001
67 #define PIN_INTERRUPT_FALLING 0b1010
68 #define PIN_INTERRUPT_EDGE 0b1011
69 
75 #define LPTMR_CLKEN() (bit_set32(&SIM->SCGC5, SIM_SCGC5_LPTMR_SHIFT))
76 #define PIT_CLKEN() (bit_set32(&SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
83 #define KINETIS_PMCTRL SMC->PMCTRL
84 #define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK)
85 /* Clear LLS protection, clear VLPS, VLPW, VLPR protection */
86 /* Note: This register can only be written once after each reset, so we must
87  * enable all power modes that we wish to use. */
88 #define KINETIS_PMPROT_UNLOCK() (SMC->PMPROT |= SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK)
89 
95 #define KINETIS_POWER_MODE_NORMAL (0b000)
96 
97 #define KINETIS_POWER_MODE_VLPS (0b010)
98 
99 #define KINETIS_POWER_MODE_LLS (0b011)
100 
108 #define KINETIS_LLWU_WAKEUP_MODULE_LPTMR 0
109 
113 #define KINETIS_LLWU_IRQ LLW_IRQn
114 
118 #define LLWU_UNLOCK() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1)
119 
125 typedef enum llwu_wakeup_module {
126  KINETIS_LPM_WAKEUP_MODULE_LPTMR = 0,
127  KINETIS_LPM_WAKEUP_MODULE_CMP0 = 1,
128  KINETIS_LPM_WAKEUP_MODULE_CMP1 = 2,
129  KINETIS_LPM_WAKEUP_MODULE_CMP2 = 3,
130  KINETIS_LPM_WAKEUP_MODULE_TSI = 4,
131  KINETIS_LPM_WAKEUP_MODULE_RTC_ALARM = 5,
132  KINETIS_LPM_WAKEUP_MODULE_RESERVED = 6,
133  KINETIS_LPM_WAKEUP_MODULE_RTC_SECONDS = 7,
134  KINETIS_LPM_WAKEUP_MODULE_END,
136 
142 typedef enum llwu_wakeup_pin {
143  KINETIS_LPM_WAKEUP_PIN_PTE1 = 0,
144  KINETIS_LPM_WAKEUP_PIN_PTE2 = 1,
145  KINETIS_LPM_WAKEUP_PIN_PTE4 = 2,
146  KINETIS_LPM_WAKEUP_PIN_PTA4 = 3,
147  KINETIS_LPM_WAKEUP_PIN_PTA13 = 4,
148  KINETIS_LPM_WAKEUP_PIN_PTB0 = 5,
149  KINETIS_LPM_WAKEUP_PIN_PTC1 = 6,
150  KINETIS_LPM_WAKEUP_PIN_PTC3 = 7,
151  KINETIS_LPM_WAKEUP_PIN_PTC4 = 8,
152  KINETIS_LPM_WAKEUP_PIN_PTC5 = 9,
153  KINETIS_LPM_WAKEUP_PIN_PTC6 = 10,
154  KINETIS_LPM_WAKEUP_PIN_PTC11 = 11,
155  KINETIS_LPM_WAKEUP_PIN_PTD0 = 12,
156  KINETIS_LPM_WAKEUP_PIN_PTD2 = 13,
157  KINETIS_LPM_WAKEUP_PIN_PTD4 = 14,
158  KINETIS_LPM_WAKEUP_PIN_PTD6 = 15,
159  KINETIS_LPM_WAKEUP_PIN_END
161 
164 #ifdef __cplusplus
165 }
166 #endif
167 
168 #endif /* CPU_CONF_H */
169 
enum llwu_wakeup_pin llwu_wakeup_pin_t
enum that maps physical pins to wakeup pin numbers in LLWU module
Common CPU definitione for Cortex-M family based MCUs.
llwu_wakeup_pin
enum that maps physical pins to wakeup pin numbers in LLWU module
llwu_wakeup_module
Internal modules whose interrupts are mapped to LLWU wake up sources.
enum llwu_wakeup_module llwu_wakeup_module_t
Internal modules whose interrupts are mapped to LLWU wake up sources.