cpu/k60/include/cpu_conf.h
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1 /*
2  * Copyright (C) 2015 Eistec AB
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
21 #ifndef CPU_CONF_H
22 #define CPU_CONF_H
23 
24 #include "cpu_conf_common.h"
25 
26 #ifdef __cplusplus
27 extern "C"
28 {
29 #endif
30 
31 #include <stdint.h>
32 
33 #if defined(CPU_MODEL_MK60DN512VLL10) || defined(CPU_MODEL_MK60DN256VLL10)
34 #include "vendor/MK60D10.h"
35 
38 #define K60_EXPECTED_CPUID 0x410fc241u
39 
40 /* K60 rev 2.x replaced the RNG module in 1.x by the RNGA PRNG module */
41 #define KINETIS_RNGA (RNG)
42 #else
43 #error Unknown CPU model. Update Makefile.include in the board directory.
44 #endif
45 
50 #define CPU_DEFAULT_IRQ_PRIO (1U)
51 #define CPU_IRQ_NUMOF (104U)
52 #define CPU_FLASH_BASE (0x00000000)
53 
59 #define PIN_MUX_FUNCTION_ANALOG 0
60 #define PIN_MUX_FUNCTION_GPIO 1
61 
66 #define PIN_INTERRUPT_RISING 0b1001
67 #define PIN_INTERRUPT_FALLING 0b1010
68 #define PIN_INTERRUPT_EDGE 0b1011
69 
73 #define PORTA_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
74 #define PORTB_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
75 #define PORTC_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
76 #define PORTD_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
77 #define PORTE_CLOCK_GATE (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
78 
84 #define LPTIMER_DEV (LPTMR0)
85 #define LPTIMER_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 1)
86 #define LPTIMER_CLKDIS() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 0)
87 #define LPTIMER_CLKSRC_MCGIRCLK 0
88 #define LPTIMER_CLKSRC_LPO 1
89 #define LPTIMER_CLKSRC_ERCLK32K 2
90 #define LPTIMER_CLKSRC_OSCERCLK 3
92 #ifndef LPTIMER_CLKSRC
93 #define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K
94 #endif
95 
96 #if (LPTIMER_CLKSRC == LPTIMER_CLKSRC_MCGIRCLK)
97 #define LPTIMER_CLK_PRESCALE 1
98 #define LPTIMER_SPEED 1000000
99 #elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_OSCERCLK)
100 #define LPTIMER_CLK_PRESCALE 1
101 #define LPTIMER_SPEED 1000000
102 #elif (LPTIMER_CLKSRC == LPTIMER_CLKSRC_ERCLK32K)
103 #define LPTIMER_CLK_PRESCALE 0
104 #define LPTIMER_SPEED 32768
105 #else
106 #define LPTIMER_CLK_PRESCALE 0
107 #define LPTIMER_SPEED 1000
108 #endif
109 
111 #define LPTIMER_IRQ_PRIO 1
112 
113 #define LPTIMER_IRQ_CHAN LPTMR0_IRQn
114 
121 #define KINETIS_PMCTRL SMC->PMCTRL
122 #define KINETIS_PMCTRL_SET_MODE(x) (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK)
123 /* Clear LLS protection, clear VLPS, VLPW, VLPR protection */
124 /* Note: This register can only be written once after each reset, so we must
125  * enable all power modes that we wish to use. */
126 #define KINETIS_PMPROT_UNLOCK() (SMC->PMPROT |= SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK)
127 
133 #define KINETIS_POWER_MODE_NORMAL (0b000)
134 
135 #define KINETIS_POWER_MODE_VLPS (0b010)
136 
137 #define KINETIS_POWER_MODE_LLS (0b011)
138 
146 #define KINETIS_LLWU_WAKEUP_MODULE_LPTMR 0
147 
151 #define KINETIS_LLWU_IRQ LLW_IRQn
152 
156 #define LLWU_UNLOCK() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1)
157 
163 typedef enum llwu_wakeup_module {
164  KINETIS_LPM_WAKEUP_MODULE_LPTMR = 0,
165  KINETIS_LPM_WAKEUP_MODULE_CMP0 = 1,
166  KINETIS_LPM_WAKEUP_MODULE_CMP1 = 2,
167  KINETIS_LPM_WAKEUP_MODULE_CMP2 = 3,
168  KINETIS_LPM_WAKEUP_MODULE_TSI = 4,
169  KINETIS_LPM_WAKEUP_MODULE_RTC_ALARM = 5,
170  KINETIS_LPM_WAKEUP_MODULE_RESERVED = 6,
171  KINETIS_LPM_WAKEUP_MODULE_RTC_SECONDS = 7,
172  KINETIS_LPM_WAKEUP_MODULE_END,
174 
180 typedef enum llwu_wakeup_pin {
181  KINETIS_LPM_WAKEUP_PIN_PTE1 = 0,
182  KINETIS_LPM_WAKEUP_PIN_PTE2 = 1,
183  KINETIS_LPM_WAKEUP_PIN_PTE4 = 2,
184  KINETIS_LPM_WAKEUP_PIN_PTA4 = 3,
185  KINETIS_LPM_WAKEUP_PIN_PTA13 = 4,
186  KINETIS_LPM_WAKEUP_PIN_PTB0 = 5,
187  KINETIS_LPM_WAKEUP_PIN_PTC1 = 6,
188  KINETIS_LPM_WAKEUP_PIN_PTC3 = 7,
189  KINETIS_LPM_WAKEUP_PIN_PTC4 = 8,
190  KINETIS_LPM_WAKEUP_PIN_PTC5 = 9,
191  KINETIS_LPM_WAKEUP_PIN_PTC6 = 10,
192  KINETIS_LPM_WAKEUP_PIN_PTC11 = 11,
193  KINETIS_LPM_WAKEUP_PIN_PTD0 = 12,
194  KINETIS_LPM_WAKEUP_PIN_PTD2 = 13,
195  KINETIS_LPM_WAKEUP_PIN_PTD4 = 14,
196  KINETIS_LPM_WAKEUP_PIN_PTD6 = 15,
197  KINETIS_LPM_WAKEUP_PIN_END
199 
206 /* Generic bitband conversion routine */
214 #define BITBAND_ADDR(addr, bit) ((((uint32_t) (addr)) & 0xF0000000u) + 0x2000000 + ((((uint32_t) (addr)) & 0xFFFFF) << 5) + ((bit) << 2))
215 
222 #define BITBAND_VAR32(var, bit) (*((uint32_t volatile*) BITBAND_ADDR(&(var), (bit))))
223 
230 #define BITBAND_VAR16(var, bit) (*((uint16_t volatile*) BITBAND_ADDR(&(var), (bit))))
231 
238 #define BITBAND_VAR8(var, bit) (*((uint8_t volatile*) BITBAND_ADDR(&(var), (bit))))
239 
241 #ifdef __cplusplus
242 }
243 #endif
244 
245 #endif /* CPU_CONF_H */
246 
enum llwu_wakeup_pin llwu_wakeup_pin_t
enum that maps physical pins to wakeup pin numbers in LLWU module
Common CPU definitione for Cortex-M family based MCUs.
llwu_wakeup_pin
enum that maps physical pins to wakeup pin numbers in LLWU module
llwu_wakeup_module
Internal modules whose interrupts are mapped to LLWU wake up sources.
enum llwu_wakeup_module llwu_wakeup_module_t
Internal modules whose interrupts are mapped to LLWU wake up sources.