cpu/k60/include/cpu_conf.h File Reference

Implementation specific CPU configuration options. More...

Detailed Description

#include "cpu_conf_common.h"
#include <stdint.h>
+ Include dependency graph for cpu/k60/include/cpu_conf.h:

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Macros

#define KINETIS_LLWU_WAKEUP_MODULE_LPTMR   0
 Wake up source number for the LPTMR0. More...
 
#define KINETIS_LLWU_IRQ   LLW_IRQn
 IRQn name to enable LLWU IRQ in NVIC.
 
#define LLWU_UNLOCK()   (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_LLWU_SHIFT) = 1)
 Enable clock gate on LLWU module.
 
#define CPU_DEFAULT_IRQ_PRIO   (1U)
 ARM Cortex-M specific CPU configuration.
 
#define CPU_IRQ_NUMOF   (104U)
 
#define CPU_FLASH_BASE   (0x00000000)
 
GPIO pin mux function numbers
#define PIN_MUX_FUNCTION_ANALOG   0
 
#define PIN_MUX_FUNCTION_GPIO   1
 
GPIO interrupt flank settings
#define PIN_INTERRUPT_RISING   0b1001
 
#define PIN_INTERRUPT_FALLING   0b1010
 
#define PIN_INTERRUPT_EDGE   0b1011
 
PORT module clock gates
#define PORTA_CLOCK_GATE   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT))
 
#define PORTB_CLOCK_GATE   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT))
 
#define PORTC_CLOCK_GATE   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT))
 
#define PORTD_CLOCK_GATE   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT))
 
#define PORTE_CLOCK_GATE   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT))
 
Clock settings for the LPTMR0 timer
#define LPTIMER_DEV   (LPTMR0)
 LPTIMER hardware module.
 
#define LPTIMER_CLKEN()   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 1)
 Enable LPTMR0 clock gate.
 
#define LPTIMER_CLKDIS()   (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_LPTIMER_SHIFT) = 0)
 Disable LPTMR0 clock gate.
 
#define LPTIMER_CLKSRC_MCGIRCLK   0
 internal reference clock (4MHz)
 
#define LPTIMER_CLKSRC_LPO   1
 PMC 1kHz output.
 
#define LPTIMER_CLKSRC_ERCLK32K   2
 RTC clock 32768Hz.
 
#define LPTIMER_CLKSRC_OSCERCLK   3
 system oscillator output, clock from RF-Part
 
#define LPTIMER_CLKSRC   LPTIMER_CLKSRC_ERCLK32K
 default clock source
 
#define LPTIMER_CLK_PRESCALE   0
 
#define LPTIMER_SPEED   32768
 
#define LPTIMER_IRQ_PRIO   1
 IRQ priority for hwtimer interrupts.
 
#define LPTIMER_IRQ_CHAN   LPTMR0_IRQn
 IRQ channel for hwtimer interrupts.
 
Power mode hardware details
#define KINETIS_PMCTRL   SMC->PMCTRL
 
#define KINETIS_PMCTRL_SET_MODE(x)   (KINETIS_PMCTRL = SMC_PMCTRL_STOPM(x) | SMC_PMCTRL_LPWUI_MASK)
 
#define KINETIS_PMPROT_UNLOCK()   (SMC->PMPROT |= SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK)
 
STOP mode bitfield values
#define KINETIS_POWER_MODE_NORMAL   (0b000)
 Normal STOP.
 
#define KINETIS_POWER_MODE_VLPS   (0b010)
 VLPS STOP.
 
#define KINETIS_POWER_MODE_LLS   (0b011)
 LLS STOP.
 
Bit band macros
#define BITBAND_ADDR(addr, bit)   ((((uint32_t) (addr)) & 0xF0000000u) + 0x2000000 + ((((uint32_t) (addr)) & 0xFFFFF) << 5) + ((bit) << 2))
 Convert bit-band region address and bit number to bit-band alias address. More...
 
#define BITBAND_VAR32(var, bit)   (*((uint32_t volatile*) BITBAND_ADDR(&(var), (bit))))
 Bitband 32 bit access to variable stored in SRAM_U. More...
 
#define BITBAND_VAR16(var, bit)   (*((uint16_t volatile*) BITBAND_ADDR(&(var), (bit))))
 Bitband 16 bit access to variable stored in SRAM_U. More...
 
#define BITBAND_VAR8(var, bit)   (*((uint8_t volatile*) BITBAND_ADDR(&(var), (bit))))
 Bitband 8 bit access to variable stored in SRAM_U. More...
 

Typedefs

typedef enum llwu_wakeup_module llwu_wakeup_module_t
 Internal modules whose interrupts are mapped to LLWU wake up sources. More...
 
typedef enum llwu_wakeup_pin llwu_wakeup_pin_t
 enum that maps physical pins to wakeup pin numbers in LLWU module More...
 

Enumerations

enum  llwu_wakeup_module {
  KINETIS_LPM_WAKEUP_MODULE_LPTMR = 0, KINETIS_LPM_WAKEUP_MODULE_CMP0 = 1, KINETIS_LPM_WAKEUP_MODULE_CMP1 = 2, KINETIS_LPM_WAKEUP_MODULE_CMP2 = 3,
  KINETIS_LPM_WAKEUP_MODULE_TSI = 4, KINETIS_LPM_WAKEUP_MODULE_RTC_ALARM = 5, KINETIS_LPM_WAKEUP_MODULE_RESERVED = 6, KINETIS_LPM_WAKEUP_MODULE_RTC_SECONDS = 7,
  KINETIS_LPM_WAKEUP_MODULE_END
}
 Internal modules whose interrupts are mapped to LLWU wake up sources. More...
 
enum  llwu_wakeup_pin {
  KINETIS_LPM_WAKEUP_PIN_PTE1 = 0, KINETIS_LPM_WAKEUP_PIN_PTE2 = 1, KINETIS_LPM_WAKEUP_PIN_PTE4 = 2, KINETIS_LPM_WAKEUP_PIN_PTA4 = 3,
  KINETIS_LPM_WAKEUP_PIN_PTA13 = 4, KINETIS_LPM_WAKEUP_PIN_PTB0 = 5, KINETIS_LPM_WAKEUP_PIN_PTC1 = 6, KINETIS_LPM_WAKEUP_PIN_PTC3 = 7,
  KINETIS_LPM_WAKEUP_PIN_PTC4 = 8, KINETIS_LPM_WAKEUP_PIN_PTC5 = 9, KINETIS_LPM_WAKEUP_PIN_PTC6 = 10, KINETIS_LPM_WAKEUP_PIN_PTC11 = 11,
  KINETIS_LPM_WAKEUP_PIN_PTD0 = 12, KINETIS_LPM_WAKEUP_PIN_PTD2 = 13, KINETIS_LPM_WAKEUP_PIN_PTD4 = 14, KINETIS_LPM_WAKEUP_PIN_PTD6 = 15,
  KINETIS_LPM_WAKEUP_PIN_END
}
 enum that maps physical pins to wakeup pin numbers in LLWU module More...
 

Macro Definition Documentation

#define BITBAND_ADDR (   addr,
  bit 
)    ((((uint32_t) (addr)) & 0xF0000000u) + 0x2000000 + ((((uint32_t) (addr)) & 0xFFFFF) << 5) + ((bit) << 2))
Parameters
[in]addrbase address in non-bit-banded memory
[in]bitbit number within the word
Returns
Address of the bit within the bit-band memory region

Definition at line 214 of file cpu/k60/include/cpu_conf.h.

#define BITBAND_VAR16 (   var,
  bit 
)    (*((uint16_t volatile*) BITBAND_ADDR(&(var), (bit))))
Note
SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
var must be declared 'volatile'

Definition at line 230 of file cpu/k60/include/cpu_conf.h.

#define BITBAND_VAR32 (   var,
  bit 
)    (*((uint32_t volatile*) BITBAND_ADDR(&(var), (bit))))
Note
SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
var must be declared 'volatile'

Definition at line 222 of file cpu/k60/include/cpu_conf.h.

#define BITBAND_VAR8 (   var,
  bit 
)    (*((uint8_t volatile*) BITBAND_ADDR(&(var), (bit))))
Note
SRAM_L is not bit band aliased on the K60, only SRAM_U (0x20000000 and up)
var must be declared 'volatile'

Definition at line 238 of file cpu/k60/include/cpu_conf.h.