cfg_i2c1_pb8_pb9.h
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1 /*
2  * Copyright (C) 2018 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef CFG_I2C1_PB8_PB9_H
20 #define CFG_I2C1_PB8_PB9_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 static const i2c_conf_t i2c_config[] = {
33  {
34  .dev = I2C1,
35  .speed = I2C_SPEED_NORMAL,
36  .scl_pin = GPIO_PIN(PORT_B, 8),
37  .sda_pin = GPIO_PIN(PORT_B, 9),
38 #if CPU_FAM_STM32F0
39  .scl_af = GPIO_AF1,
40  .sda_af = GPIO_AF1,
41 #else
42  .scl_af = GPIO_AF4,
43  .sda_af = GPIO_AF4,
44 #endif
45  .bus = APB1,
46 #if CPU_FAM_STM32F4 || CPU_FAM_STM32F2
47  .rcc_mask = RCC_APB1ENR_I2C1EN,
48  .clk = CLOCK_APB1,
49  .irqn = I2C1_EV_IRQn,
50 #elif CPU_FAM_STM32L4
51  .rcc_mask = RCC_APB1ENR1_I2C1EN,
52  .irqn = I2C1_ER_IRQn,
53 #elif CPU_FAM_STM32F7
54  .rcc_mask = RCC_APB1ENR_I2C1EN,
55  .irqn = I2C1_ER_IRQn,
56 #elif CPU_FAM_STM32F0 || CPU_FAM_STM32L0
57  .rcc_mask = RCC_APB1ENR_I2C1EN,
58 #if CPU_FAM_STM32F0
59  .rcc_sw_mask = RCC_CFGR3_I2C1SW,
60 #endif
61  .irqn = I2C1_IRQn,
62 #endif
63  }
64 };
65 
66 #if CPU_FAM_STM32F4 || CPU_FAM_STM32F2
67 #define I2C_0_ISR isr_i2c1_ev
68 #elif CPU_FAM_STM32L4 || CPU_FAM_STM32F7
69 #define I2C_0_ISR isr_i2c1_er
70 #elif CPU_FAM_STM32F0 || CPU_FAM_STM32L0
71 #define I2C_0_ISR isr_i2c1
72 #endif
73 
74 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
75 
77 #ifdef __cplusplus
78 }
79 #endif
80 
81 #endif /* CFG_I2C1_PB8_PB9_H */
82 
use alternate function 4
I2C configuration options.
Definition: periph_cpu.h:128
APB1 bus.
use alternate function 1
static const i2c_conf_t i2c_config[]
Static array with configuration for declared I2C devices.
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:240
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
normal mode: ~100 kbit/s
Definition: i2c.h:183
port B
Definition: periph_cpu.h:37