cfg_clock_216_8_1.h
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1 /*
2  * Copyright (C) 2019 Otto-von-Guericke-Universit├Ąt Magdeburg
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
24 #ifndef F7_CFG_CLOCK_216_8_1_H
25 #define F7_CFG_CLOCK_216_8_1_H
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
31 /* give the target core clock (HCLK) frequency [in Hz],
32  * maximum: 216MHz */
33 #define CLOCK_CORECLOCK (216000000U)
34 /* 0: no external high speed crystal available
35  * else: actual crystal frequency [in Hz] */
36 #define CLOCK_HSE (8000000U)
37 /* 0: no external low speed crystal available,
38  * 1: external crystal available (always 32.768kHz) */
39 #define CLOCK_LSE (1U)
40 /* peripheral clock setup */
41 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
42 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
43 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
44 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
45 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
46 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
47 
48 /* Main PLL factors */
49 #define CLOCK_PLL_M (4)
50 #define CLOCK_PLL_N (216)
51 #define CLOCK_PLL_P (2)
52 #define CLOCK_PLL_Q (9)
53 
54 #ifdef __cplusplus
55 }
56 #endif
57 
58 #endif /* F7_CFG_CLOCK_216_8_1_H */
59