cfg_clock_216_8_1.h File Reference

Configure STM32F7 clock to 216MHz and 8MHz HSE using PLL with LSE. More...

Detailed Description

Configure STM32F7 clock to 216MHz and 8MHz HSE using PLL with LSE.

Author
Marian Buschsieweke maria.nosp@m.n.bu.nosp@m.schsi.nosp@m.ewek.nosp@m.e@ovg.nosp@m.u.de
Note
This is auto-generated from cpu/stm32_common/dist/clk_conf/clk_conf.c

Definition in file cfg_clock_216_8_1.h.

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Go to the source code of this file.

#define CLOCK_CORECLOCK   (216000000U)
 
#define CLOCK_HSE   (8000000U)
 
#define CLOCK_LSE   (1U)
 
#define CLOCK_AHB_DIV   RCC_CFGR_HPRE_DIV1
 
#define CLOCK_AHB   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB1_DIV   RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
 
#define CLOCK_APB1   (CLOCK_CORECLOCK / 4)
 
#define CLOCK_APB2_DIV   RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
 
#define CLOCK_APB2   (CLOCK_CORECLOCK / 2)
 
#define CLOCK_PLL_M   (4)
 
#define CLOCK_PLL_N   (216)
 
#define CLOCK_PLL_P   (2)
 
#define CLOCK_PLL_Q   (9)