cfg_clock_168_8_common.h File Reference

Configure STM32F4 clock to 168MHz using PLL. More...

Detailed Description

Configure STM32F4 clock to 168MHz using PLL.

Author
Hauke Petersen hauke.nosp@m..pet.nosp@m.ersen.nosp@m.@fu-.nosp@m.berli.nosp@m.n.de

Definition in file cfg_clock_168_8_common.h.

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Clock settings

Note
This is auto-generated from cpu/stm32_common/dist/clk_conf/clk_conf.c
#define CLOCK_CORECLOCK   (168000000U)
 
#define CLOCK_HSE   (8000000U)
 
#define CLOCK_AHB_DIV   RCC_CFGR_HPRE_DIV1
 
#define CLOCK_AHB   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB1_DIV   RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
 
#define CLOCK_APB1   (CLOCK_CORECLOCK / 4)
 
#define CLOCK_APB2_DIV   RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
 
#define CLOCK_APB2   (CLOCK_CORECLOCK / 2)
 
#define CLOCK_PLL_M   (4)
 
#define CLOCK_PLL_N   (168)
 
#define CLOCK_PLL_P   (2)
 
#define CLOCK_PLL_Q   (7)