CC26xx/CC13xx MCU I/O register definitions. More...

Detailed Description

CC26xx/CC13xx MCU I/O register definitions.

Author: Leon George leon@.nosp@m.geor.nosp@m.gemai.nosp@m.l.eu

Definition in file cc26xx_cc13xx_i2c.h.

#include "cc26xx_cc13xx.h"

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Data Structures
struct	i2c_regs_t
	I2C registers. More...

Macros
#define	I2C ((i2c_regs_t *) (I2C_BASE))
	I2C register bank.

#define	MCR_MFE 0x00000010
	I2C master function enable.

#define	MTPR_TPR_100KHZ 0x00000017
	SCL clock period set to 100 kHZ.

#define	MSA_RS 0x00000001
	Receive or Send.

#define	MSTAT_BUSBSY 0x00000040
	Bus busy.

#define	MSTAT_IDLE 0x00000020
	I2C idle.

#define	MSTAT_ARBLST 0x00000010
	Arbitration lost.

#define	MSTAT_DATACK_N 0x00000008
	Data Was Not Acknowledge.

#define	MSTAT_ADRACK_N 0x00000004
	Address Was Not Acknowledge.

#define	MSTAT_ERR 0x00000002
	Error.

#define	MSTAT_BUSY 0x00000001
	I2C busy.

#define	MCTRL_ACK 0x00000008
	Data acknowledge enable.

#define	MCTRL_STOP 0x00000004
	This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition.

#define	MCTRL_START 0x00000002
	This bit-field generates the Start or Repeated Start condition.

#define	MCTRL_RUN 0x00000001
	I2C master enable.

#define	I2C_BASE (PERIPH_BASE + 0x2000)
	I2C base address.

Macro Definition Documentation

◆ I2C

#define I2C ((i2c_regs_t *) (I2C_BASE))

I2C register bank.

Definition at line 195 of file cc26xx_cc13xx_i2c.h.

◆ MCR_MFE

#define MCR_MFE 0x00000010

I2C master function enable.

0h = Master mode is disabled. 1h = Master mode is enabled

Definition at line 62 of file cc26xx_cc13xx_i2c.h.

◆ MCTRL_ACK

#define MCTRL_ACK 0x00000008

Data acknowledge enable.

0: The received data byte is not acknowledged automatically by the master. 1: The received data byte is acknowledged automatically by the master. This bit-field must be cleared when the I2C bus controller requires no further data to be transmitted from the slave transmitter. 0h = Disable acknowledge 1h = Enable acknowledge

Definition at line 158 of file cc26xx_cc13xx_i2c.h.

◆ MCTRL_RUN

#define MCTRL_RUN 0x00000001

I2C master enable.

0: The master is disabled. 1: The master is enabled to transmit or receive data. 0h = Disable Master 1h = Enable Master

Definition at line 186 of file cc26xx_cc13xx_i2c.h.

◆ MCTRL_START

#define MCTRL_START 0x00000002

This bit-field generates the Start or Repeated Start condition.

0: The controller does not generate the Start condition. 1: The controller generates the Start condition. 0h = Disable START 1h = Enable START

Definition at line 177 of file cc26xx_cc13xx_i2c.h.

◆ MCTRL_STOP

#define MCTRL_STOP 0x00000004

This bit-field determines if the cycle stops at the end of the data cycle or continues on to a repeated START condition.

0: The controller does not generate the Stop condition. 1: The controller generates the Stop condition. 0h = Disable STOP 1h = Enable STOP

Definition at line 168 of file cc26xx_cc13xx_i2c.h.

◆ MSA_RS

#define MSA_RS 0x00000001

Receive or Send.

This bit-field specifies if the next operation is a receive (high) or a transmit/send (low) from the addressed slave SA. 0h = Transmit/send data to slave 1h = Receive data from slave

Definition at line 86 of file cc26xx_cc13xx_i2c.h.

◆ MSTAT_ADRACK_N

#define MSTAT_ADRACK_N 0x00000004

Address Was Not Acknowledge.

0: The transmitted address was acknowledged. 1: The transmitted address was not acknowledged.

Definition at line 123 of file cc26xx_cc13xx_i2c.h.

◆ MSTAT_ARBLST

#define MSTAT_ARBLST 0x00000010

Arbitration lost.

0: The I2C controller won arbitration. 1: The I2C controller lost arbitration.

Definition at line 109 of file cc26xx_cc13xx_i2c.h.

◆ MSTAT_BUSBSY

#define MSTAT_BUSBSY 0x00000040

Bus busy.

0: The I2C bus is idle. 1: The I2C bus is busy. The bit changes based on the MCTRL.START and MCTRL.STOP conditions.

Definition at line 95 of file cc26xx_cc13xx_i2c.h.

◆ MSTAT_BUSY

#define MSTAT_BUSY 0x00000001

I2C busy.

0: The controller is idle. 1: The controller is busy. When this bit-field is set, the other status bits are not valid.

Note: The I2C controller requires four SYSBUS clock cycles to assert the BUSY status after I2C master operation has been initiated through MCTRL register. Hence after programming MCTRL register, application is requested to wait for four SYSBUS clock cycles before issuing a controller status inquiry through MSTAT register. Any prior inquiry would result in wrong status being reported.

Definition at line 145 of file cc26xx_cc13xx_i2c.h.

◆ MSTAT_DATACK_N

#define MSTAT_DATACK_N 0x00000008

Data Was Not Acknowledge.

0: The transmitted data was acknowledged. 1: The transmitted data was not acknowledged.

Definition at line 116 of file cc26xx_cc13xx_i2c.h.

◆ MSTAT_ERR

#define MSTAT_ERR 0x00000002

Error.

0: No error was detected on the last operation. 1: An error occurred on the last operation.

Definition at line 130 of file cc26xx_cc13xx_i2c.h.

◆ MSTAT_IDLE

#define MSTAT_IDLE 0x00000020

I2C idle.

0: The I2C controller is not idle. 1: The I2C controller is idle.

Definition at line 102 of file cc26xx_cc13xx_i2c.h.

◆ MTPR_TPR_100KHZ

#define MTPR_TPR_100KHZ 0x00000017

SCL clock period set to 100 kHZ.

{PERDMACLK / [2 × (SCL_LP + SCL_HP) × SCL_CLK]} – 1 with SCL_LP==6 && SCL_HP==4 use 0x17 for 100kHZ with 48MHZ CPU clock This field specifies the period of the SCL clock. SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD where: SCL_PRD is the SCL line period (I2C clock). TPR is the timer period register value (range of 1 to 127) SCL_LP is the SCL low period (fixed at 6). SCL_HP is the SCL high period (fixed at 4). CLK_PRD is the system clock period in ns.

Definition at line 77 of file cc26xx_cc13xx_i2c.h.