cc26xx_cc13xx.h
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1 /*
2  * Copyright (C) 2016 Leon George
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef CC26XX_CC13XX_H
21 #define CC26XX_CC13XX_H
22 
23 #include <stdint.h>
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
29 typedef volatile uint8_t reg8_t;
30 typedef volatile uint16_t reg16_t;
31 typedef volatile uint32_t reg32_t;
32 
36 typedef struct {
37  reg8_t LOW;
38  reg8_t HIGH;
39 } reg8_m4_t;
40 
44 typedef reg16_t reg8_m8_t;
45 
49 typedef struct {
50  reg32_t LOW;
51  reg32_t HIGH;
52 } reg32_m16_t;
53 
56 
58 typedef enum IRQn
59 {
60  /****** Cortex-M4 Processor Exceptions Numbers ****************************/
65  BusFault_IRQn = -11,
67  SVCall_IRQn = - 5,
69  PendSV_IRQn = - 2,
70  SysTick_IRQn = - 1,
72  /****** CC13x2 specific Interrupt Numbers *********************************/
74  I2C_IRQN = 1,
76  PKA_IRQN = 3,
78  UART0_IRQN = 5,
80  SSI0_IRQN = 7,
81  SSI1_IRQN = 8,
83  RF_HW_IRQN = 10,
85  I2S_IRQN = 12,
96  CRYPTO_IRQN = 23,
97  UDMA_IRQN = 24,
100  SW0_IRQN = 27,
103  PROG_IRQN = 30,
106  TRNG_IRQN = 33,
107 #ifdef CPU_VARIANT_X2
108  OSC_IRQN = 34,
109  AUX_TIMER2_IRQN = 35,
110  UART1_IRQN = 36,
111  BATMON_IRQN = 37,
113  IRQN_COUNT = (BATMON_IRQN + 1)
114 #else
116 #endif
117 
118 } IRQn_Type;
119 
124 #define __MPU_PRESENT 1
125 #define __NVIC_PRIO_BITS 3
126 #define __Vendor_SysTickConfig 0
128 #define RCOSC48M_FREQ 48000000
129 #define RCOSC24M_FREQ 24000000
134 #ifdef CPU_VARIANT_X2
135 #include <core_cm4.h>
136 #else
137 #include <core_cm3.h>
138 #endif
139 
144 #define FLASH_BASE 0x00000000
145 #define PERIPH_BASE 0x40000000
146 #define PERIPH_BASE_NONBUF 0x60000000
147 #define ROM_HARD_API_BASE 0x10000048
148 #define ROM_API_TABLE ((uint32_t *) 0x10000180)
150 
151 
155 #define ADI_DIR 0x00000000
156 #define ADI_SET 0x00000010
157 #define ADI_CLR 0x00000020
158 #define ADI_MASK4B 0x00000040
159 #define ADI_MASK8B 0x00000060
160 #define ADI_MASK16B 0x00000080
161 
163 #ifdef __cplusplus
164 }
165 #endif
166 
167 #endif /* CC26XX_CC13XX_H */
168 
reg32_t HIGH
High 16-bit half.
Definition: cc26xx_cc13xx.h:51
46 Dynamic Programmable interrupt (default source: PRCM)
30 Watchdog timer
Definition: cc26xx_cc13xx.h:87
3 Cortex-M4 Hard Fault Interrupt
Definition: cc26xx_cc13xx.h:63
47 AUX Comparator A
reg16_t reg8_m8_t
Masked 8-bit register.
Definition: cc26xx_cc13xx.h:44
24 SSI1 Rx and Tx
Definition: cc26xx_cc13xx.h:81
Masked 32-bit register.
Definition: cc26xx_cc13xx.h:49
26 RF Core Hardware
Definition: cc26xx_cc13xx.h:83
22 Sensor Controller software event 0, through AON domain
Definition: cc26xx_cc13xx.h:79
43 Software Event 0
reg8_t LOW
Low 4-bit half.
Definition: cc26xx_cc13xx.h:37
23 SSI0 Rx and Tx
Definition: cc26xx_cc13xx.h:80
37 Timer 3 subtimer A
Definition: cc26xx_cc13xx.h:94
40 uDMA Software
Definition: cc26xx_cc13xx.h:97
31 Timer 0 subtimer A
Definition: cc26xx_cc13xx.h:88
25 RF Command and Packet Engine 0
Definition: cc26xx_cc13xx.h:82
33 Timer 1 subtimer A
Definition: cc26xx_cc13xx.h:90
28 I2S
Definition: cc26xx_cc13xx.h:85
16 AON edge detect
Definition: cc26xx_cc13xx.h:73
reg8_t HIGH
High 4-bit half.
Definition: cc26xx_cc13xx.h:38
21 UART0 Rx and Tx
Definition: cc26xx_cc13xx.h:78
35 Timer 2 subtimer A
Definition: cc26xx_cc13xx.h:92
17 I2C
Definition: cc26xx_cc13xx.h:74
48 AUX ADC IRQ
1 Reset Handler
Definition: cc26xx_cc13xx.h:61
enum IRQn IRQn_Type
interrupt number definition
6 Cortex-M4 Usage Fault Interrupt
Definition: cc26xx_cc13xx.h:66
Masked 8-bit register.
Definition: cc26xx_cc13xx.h:36
27 RF Core Command Acknowledge
Definition: cc26xx_cc13xx.h:84
4 Cortex-M4 Memory Management Interrupt
Definition: cc26xx_cc13xx.h:64
Number of peripheral IDs.
38 Timer 3 subtimer B
Definition: cc26xx_cc13xx.h:95
29 Sensor Controller software event 1, through AON domain
Definition: cc26xx_cc13xx.h:86
14 Cortex-M4 Pend SV Interrupt
Definition: cc26xx_cc13xx.h:69
5 Cortex-M4 Bus Fault Interrupt
Definition: cc26xx_cc13xx.h:65
36 Timer 2 subtimer B
Definition: cc26xx_cc13xx.h:93
IRQn
Interrupt Number Definition.
Definition: cc2538.h:33
34 Timer 1 subtimer B
Definition: cc26xx_cc13xx.h:91
41 uDMA Error
Definition: cc26xx_cc13xx.h:98
39 Crypto Core Result available
Definition: cc26xx_cc13xx.h:96
19 PKA interrupt
Definition: cc26xx_cc13xx.h:76
42 Flash controller
Definition: cc26xx_cc13xx.h:99
45 AON programmable 0
18 RF Command and Packet Engine 1
Definition: cc26xx_cc13xx.h:75
reg32_t LOW
Low 16-bit half.
Definition: cc26xx_cc13xx.h:50
12 Cortex-M4 Debug Monitor Interrupt
Definition: cc26xx_cc13xx.h:68
15 Cortex-M4 System Tick Interrupt
Definition: cc26xx_cc13xx.h:70
44 AUX combined event, directly to MCU domain
49 TRNG event
32 Timer 0 subtimer B
Definition: cc26xx_cc13xx.h:89
11 Cortex-M4 SV Call Interrupt
Definition: cc26xx_cc13xx.h:67
20 AON RTC
Definition: cc26xx_cc13xx.h:77
2 Non Maskable Interrupt
Definition: cc26xx_cc13xx.h:62