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cc26x0_prcm.h
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1 /*
2  * Copyright (C) 2016 Leon George
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
17 #ifndef CC26x0_PRCM_H
18 #define CC26x0_PRCM_H
19 
20 #include <cc26x0.h>
21 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
26 
30 typedef struct {
31  reg32_t CTL0;
32  reg32_t CTL1;
33  reg32_t RADCEXTCFG;
34  reg32_t AMPCOMPCTL;
35  reg32_t AMPCOMPTH1;
36  reg32_t AMPCOMPTH2;
37  reg32_t ANABYPASSVAL1;
38  reg32_t ANABYPASSVAL2;
39  reg32_t ATESTCTL;
41  reg32_t XOSCHFCTL;
42  reg32_t LFOSCCTL;
43  reg32_t RCOSCHFCTL;
44  reg32_t STAT0;
45  reg32_t STAT1;
46  reg32_t STAT2;
48 
53 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_RCOSC 0x0
54 #define DDI_0_OSC_CTL0_SCLK_HF_SRC_SEL_XOSC 0x1
55 #define DDI_0_OSC_CTL0_SCLK_MF_SRC_SEL 0x2
56 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_mask 0x6
57 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_RCOSC 0x0
58 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_HF_XOSC 0x4
59 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_RCOSC 0x8
60 #define DDI_0_OSC_CTL0_SCLK_LF_SRC_SEL_LF_XOSC 0xC
61 #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_mask 0x60
62 #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_HF 0x00 /* 31.25kHz */
63 #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_HF 0x20 /* 31.25kHz */
64 #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_RCOSC_LF 0x40 /* 32kHz */
65 #define DDI_0_OSC_CTL0_ACLK_REF_SRC_SEL_XOSC_LF 0x60 /* 32.768kHz */
66 #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_mask 0x180
67 #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_HF 0x000 /* 48MHz */
68 #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_RCOSC_LF 0x080 /* 48MHz */
69 #define DDI_0_OSC_CTL0_ACLK_TDC_SRC_SEL_XOSC_HF 0x100 /* 24MHz */
70 #define DDI_0_OSC_CTL0_CLK_LOSS_EN 0x200 /* enable clock loss detection */
71 #define DDI_0_OSC_CTL0_XOSC_LF_DIG_BYPASS 0x400 /* bypass XOSC_LF and use digital input clock from AON foor xosx_lf (precuations in datasheet) */
72 #define DDI_0_OSC_CTL0_XOSC_HF_POWER_MODE 0x800
73 #define DDI_0_OSC_CTL0_RCOSC_LF_TRIMMED 0x1000
74 #define DDI_0_OSC_CTL0_ALLOW_SCLK_HF_SWITCHING 0x10000
75 #define DDI_0_OSC_CTL0_FORCE_KICKSTART_EN 0x400000
76 #define DDI_0_OSC_CTL0_DOUBLER_RESET_DURATION 0x2000000
77 #define DDI_0_OSC_CTL0_DOUBLER_START_DURATION_mask 0x6000000
78 #define DDI_0_OSC_CTL0_BYPASS_RCOSC_LF_CLK_QUAL 0x10000000
79 #define DDI_0_OSC_CTL0_BYPASS_XOSC_LF_CLK_QUAL 0x20000000
80 #define DDI_0_OSC_CTL0_XTAL_IS_24M 0x80000000
81 
86 #define DDI0_OSC_BASE 0x400CA000
88 
89 #define DDI_0_OSC ((ddi0_osc_regs_t *) (DDI0_OSC_BASE))
95 typedef struct {
96  reg32_t PWRCTL;
97  reg32_t RESETCTL;
98  reg32_t SLEEPCTL;
100 
104 #define AON_SYSCTL_BASE 0x40090000
106 
107 #define AON_SYSCTL ((aon_sysctl_regs_t *) (AON_SYSCTL_BASE))
113 typedef struct {
114  reg32_t MCUCLK;
115  reg32_t AUXCLK;
116  reg32_t MCUCFG;
117  reg32_t AUXCFG;
118  reg32_t AUXCTL;
119  reg32_t PWRSTAT;
120  reg32_t __reserved1;
121  reg32_t SHUTDOWN;
122  reg32_t CTL0;
123  reg32_t CTL1;
124  reg32_t __reserved2[2];
125  reg32_t RECHARGECFG;
126  reg32_t RECHARGESTAT;
127  reg32_t __reserved3;
128  reg32_t OSCCFG;
129  reg32_t JTAGCFG;
130  reg32_t JTAGUSERCODE;
132 
137 #define MCUCLK_PWR_DWN_SRC 0x1 /* SCLK_LF in powerdown (no clock elsewise) */
138 #define MCUCLK_PWR_DWN_SRC_mask 0x3
139 #define MCUCLK_RCOSC_HF_CAL_DONE 0x4 /* set by MCU bootcode. RCOSC_HF is calibrated to 48 MHz, allowing FLASH to power up */
140 
141 #define AUXCLK_SRC_HF 0x1 /* SCLK for AUX */
142 #define AUXCLK_SRC_LF 0x4
143 #define AUXCLK_SRC_mask 0x7 /* garuanteed to be glitchless */
144 #define AUXCLK_SCLK_HF_DIV_pos 8 /* don't set while SCLK_HF active for AUX */
145 #define AUXCLK_SCLK_HF_DIV_mask 0x700 /* divisor will be 2^(value+1) */
146 #define AUXCLK_PWR_DWN_SRC_pos 11 /* SCLK_LF in powerdown when SCLK_HF is source (no clock elsewise?!) */
147 #define AUXCLK_PWR_DWN_SRC_mask 0x1800 /* datasheet is confusing.. */
148 
149 #define MCUCFG_SRAM_RET_OFF 0x0 /* no retention for any SRAM-bank */
150 #define MCUCFG_SRAM_RET_B0 0x1
151 #define MCUCFG_SRAM_RET_B01 0x3
152 #define MCUCFG_SRAM_RET_B012 0x7
153 #define MCUCFG_SRAM_RET_B0124 0xF /* retention for banks 0, 1, 2, and 3 */
154 #define MCUCFG_SRAM_FIXED_WU_EN 0x100
155 #define MCUCFG_SRAM_VIRT_OFF 0x200
156 
157 #define AUXCFG_RAM_RET_EN 0x1 /* retention for AUX_RAM bank 0. is off when otherwise in retention mode */
158 
159 #define AUXCTL_AUX_FORCE_ON 0x1
160 #define AUXCTL_SWEV 0x2
161 #define AUXCTL_SCE_RUN_EN 0x3
162 #define AUXCTL_RESET_REQ 0x80000000
163 
164 #define PWRSTAT_AUX_RESET_DONE 0x2
165 #define PWRSTAT_AUX_BUS_CONNECTED 0x4
166 #define PWRSTAT_MCU_PD_ON 0x10
167 #define PWRSTAT_AUX_PD_ON 0x20
168 #define PWRSTAT_JTAG_PD_ON 0x40
169 #define PWRSTAT_AUX_PWR_DNW 0x200
170 
171 #define SHUTDOWN_EN 0x1 /* register/cancel shutdown request */
172 
173 #define AONWUC_CTL0_MCU_SRAM_ERASE 0x4
174 #define AONWUC_CTL0_AUX_SRAM_ERASE 0x8
175 #define AONWUC_CTL0_PWR_DWN_DIS 0x10 /* disable powerdown on request */
176 
177 #define AONWUC_CTL1_MCU_WARM_RESET 0x1 /* last MCU reset was a warm reset */
178 #define AONWUC_CTL1_MCU_RESET_SRC 0x2 /* JTAG was source of last reset (MCU SW elsewise) */
179 
180 #define RECHARGECFG_PER_E_mask 0x00000007 /* number of 32KHz clocks between activation of recharge controller: */
181 #define RECHARGECFG_PER_M_mask 0x000000F8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */
182 #define RECHARGECFG_MAX_PER_E_mask 0x00000700 /* maximum period the recharge algorithm can take */
183 #define RECHARGECFG_MAX_PER_M_mask 0x0000F800 /* computed as follows: MAXCYCLES = (MAX_PER_M*16+15) * 2^(MAX_PER_E) */
184 #define RECHARGECFG_C1_mask 0x000F0000 /* i resign */
185 #define RECHARGECFG_C2_mask 0x000F0000
186 #define RECHARGECFG_ADAPTIVE_EN 0x80000000
187 
188 #define RECHARGESTAT_MAX_USED_PER_mask 0x0FFFF
189 #define RECHARGESTAT_VDDR_SMPLS_mask 0xF0000
190 
191 #define OSCCFG_PER_E_mask 0x07 /* number of 32KHz clocks between oscillator amplitude callibrations */
192 #define OSCCFG_PER_M_mask 0xF8 /* computed as follows: PERIOD = (PER_M*16+15) * 2^(PER_E) */
193 
194 #define JTAGCFG_JTAG_PD_FORCE_ON 0x10
195 
200 #define AON_WUC_BASE 0x40091000
202 
203 #define AON_WUC ((aon_wuc_regs_t *) (AON_WUC_BASE))
209 typedef struct {
210  reg32_t INFRCLKDIVR;
211  reg32_t INFRCLKDIVS;
212  reg32_t INFRCLKDIVDS;
213  reg32_t VDCTL;
214  reg32_t __reserved1[6];
215  reg32_t CLKLOADCTL;
216  reg32_t RFCCLKG;
217  reg32_t VIMSCLKG;
218  reg32_t __reserved2[2];
219  reg32_t SECDMACLKGR;
220  reg32_t SECDMACLKGS;
221  reg32_t SECDMACLKGDS;
222  reg32_t GPIOCLKGR;
223  reg32_t GPIOCLKGS;
224  reg32_t GPIOCLKGDS;
225  reg32_t GPTCLKGR;
226  reg32_t GPTCLKGS;
227  reg32_t GPTCLKGDS;
228  reg32_t I2CCLKGR;
229  reg32_t I2CCLKGS;
230  reg32_t I2CCLKGDS;
231  reg32_t UARTCLKGR;
232  reg32_t UARTCLKGS;
233  reg32_t UARTCLKGDS;
234  reg32_t SSICLKGR;
235  reg32_t SSICLKGS;
236  reg32_t SSICLKGDS;
237  reg32_t I2SCLKGR;
238  reg32_t I2SCLKGS;
239  reg32_t I2SCLKGDS;
240  reg32_t __reserved3[10];
241  reg32_t CPUCLKDIV;
242  reg32_t __reserved4[3];
243  reg32_t I2SBCLKSEL;
244  reg32_t GPTCLKDIV;
245  reg32_t I2SCLKCTL;
246  reg32_t I2SMCLKDIV;
247  reg32_t I2SBCLKDIV;
248  reg32_t I2SWCLKDIV;
249  reg32_t __reserved5[11];
250  reg32_t SWRESET;
251  reg32_t WARMRESET;
252  reg32_t __reserved6[6];
253  reg32_t PDCTL0;
254  reg32_t PDCTL0RFC;
255  reg32_t PDCTL0SERIAL;
256  reg32_t PDCTL0PERIPH;
257  reg32_t __reserved7;
258  reg32_t PDSTAT0;
259  reg32_t PDSTAT0RFC;
260  reg32_t PDSTAT0SERIAL;
261  reg32_t PDSTAT0PERIPH;
262  reg32_t __reserved8[11];
263  reg32_t PDCTL1;
264  reg32_t __reserved9;
265  reg32_t PDCTL1CPU;
266  reg32_t PDCTL1RFC;
267  reg32_t PDCTL1VIMS;
268  reg32_t __reserved10;
269  reg32_t PDSTAT1;
270  reg32_t PDSTAT1BUS;
271  reg32_t PDSTAT1RFC;
272  reg32_t PDSTAT1CPU;
273  reg32_t PDSTAT1VIMS;
274  reg32_t __reserved11[10];
275  reg32_t RFCMODESEL;
276  reg32_t __reserved12[20];
277  reg32_t RAMRETEN;
278  reg32_t __reserved13;
279  reg32_t PDRETEN;
280  reg32_t __reserved14[8];
281  reg32_t RAMHWOPT;
282 } prcm_regs_t;
283 
288 #define CLKLOADCTL_LOAD 0x1
289 #define CLKLOADCTL_LOADDONE 0x2
290 
291 #define PDCTL0_RFC_ON 0x1
292 #define PDCTL0_SERIAL_ON 0x2
293 #define PDCTL0_PERIPH_ON 0x4
294 
295 #define PDSTAT0_RFC_ON 0x1
296 #define PDSTAT0_SERIAL_ON 0x2
297 #define PDSTAT0_PERIPH_ON 0x4
298 
299 #define PDCTL1_CPU_ON 0x2
300 #define PDCTL1_RFC_ON 0x4
301 #define PDCTL1_VIMS_ON 0x8
302 
303 #define PDSTAT1_CPU_ON 0x2
304 #define PDSTAT1_RFC_ON 0x4
305 #define PDSTAT1_VIMS_ON 0x8
306 
311 #define PRCM_BASE 0x40082000
313 
314 #define PRCM ((prcm_regs_t *) (PRCM_BASE))
316 #ifdef __cplusplus
317 } /* end extern "C" */
318 #endif
319 
320 #endif /* CC26x0_PRCM_H */
321 
reg32_t I2SMCLKDIV
MCLK division ratio.
Definition: cc26x0_prcm.h:246
reg32_t PWRSTAT
power status
Definition: cc26x0_prcm.h:119
reg32_t CTL0
control 0
Definition: cc26x0_prcm.h:122
reg32_t I2SBCLKSEL
I2S clock select.
Definition: cc26x0_prcm.h:243
reg32_t RAMRETEN
memory retention control
Definition: cc26x0_prcm.h:277
reg32_t __reserved10
meh
Definition: cc26x0_prcm.h:268
AON_WUC registers.
Definition: cc26x0_prcm.h:113
reg32_t PDCTL1RFC
RFC power domain control.
Definition: cc26x0_prcm.h:266
reg32_t OSCCFG
oscillator config
Definition: cc26x0_prcm.h:128
reg32_t __reserved7
meh
Definition: cc26x0_prcm.h:257
reg32_t I2SWCLKDIV
WCLK division ratio.
Definition: cc26x0_prcm.h:248
reg32_t PDRETEN
power domain retention (undocumented)
Definition: cc26x0_prcm.h:279
reg32_t PDCTL1
power domain control
Definition: cc26x0_prcm.h:263
reg32_t CTL1
control 1
Definition: cc26x0_prcm.h:32
reg32_t RADCEXTCFG
RADC external config.
Definition: cc26x0_prcm.h:33
reg32_t ANABYPASSVAL2
analog bypass values 2
Definition: cc26x0_prcm.h:38
reg32_t PDCTL0
power domain control
Definition: cc26x0_prcm.h:253
reg32_t RESETCTL
reset management
Definition: cc26x0_prcm.h:97
reg32_t PDSTAT0SERIAL
SERIAL power domain status.
Definition: cc26x0_prcm.h:260
reg32_t INFRCLKDIVDS
infrastructure clock division factor for deep sleep mode
Definition: cc26x0_prcm.h:212
PRCM registers.
Definition: cc26x0_prcm.h:209
reg32_t PDCTL0SERIAL
SERIAL power domain control.
Definition: cc26x0_prcm.h:255
reg32_t CTL0
control 0
Definition: cc26x0_prcm.h:31
reg32_t PDSTAT1
power domain status
Definition: cc26x0_prcm.h:269
reg32_t SECDMACLKGDS
TRNG, CRYPTO, and UDMA clock gate for deep sleep mode.
Definition: cc26x0_prcm.h:221
reg32_t PWRCTL
power management
Definition: cc26x0_prcm.h:96
reg32_t CTL1
control 1
Definition: cc26x0_prcm.h:123
reg32_t PDSTAT1BUS
BUS power domain status.
Definition: cc26x0_prcm.h:270
reg32_t __reserved1
meh
Definition: cc26x0_prcm.h:120
reg32_t PDSTAT1RFC
RFC power domain status.
Definition: cc26x0_prcm.h:271
reg32_t STAT1
status 1
Definition: cc26x0_prcm.h:45
reg32_t AUXCTL
AUX control.
Definition: cc26x0_prcm.h:118
reg32_t I2CCLKGDS
I2C clock gate for deep sleep mode.
Definition: cc26x0_prcm.h:230
reg32_t GPIOCLKGS
GPIO clock gate for sleep mode.
Definition: cc26x0_prcm.h:223
reg32_t I2SCLKCTL
I2S clock control.
Definition: cc26x0_prcm.h:245
reg32_t ATESTCTL
analog test control
Definition: cc26x0_prcm.h:39
reg32_t SWRESET
SW initiated resets.
Definition: cc26x0_prcm.h:250
reg32_t SHUTDOWN
shutdown control
Definition: cc26x0_prcm.h:121
reg32_t STAT2
status 2
Definition: cc26x0_prcm.h:46
reg32_t GPTCLKGS
GPT clock gate for sleep mode.
Definition: cc26x0_prcm.h:226
reg32_t MCUCLK
MCU clock management.
Definition: cc26x0_prcm.h:114
reg32_t I2SCLKGS
I2S clock gate for sleep mode.
Definition: cc26x0_prcm.h:238
reg32_t LFOSCCTL
low frequency oscillator control
Definition: cc26x0_prcm.h:42
reg32_t AMPCOMPTH1
amplitude compensation threshold 1
Definition: cc26x0_prcm.h:35
reg32_t AMPCOMPTH2
amplitude compensation threshold 2
Definition: cc26x0_prcm.h:36
reg32_t UARTCLKGR
UART clock gate for run mode.
Definition: cc26x0_prcm.h:231
reg32_t INFRCLKDIVS
infrastructure clock division factor for sleep mode
Definition: cc26x0_prcm.h:211
reg32_t WARMRESET
WARM reset control and status.
Definition: cc26x0_prcm.h:251
reg32_t INFRCLKDIVR
infrastructure clock division factor for run mode
Definition: cc26x0_prcm.h:210
reg32_t I2SCLKGDS
I2S clock gate for deep sleep mode.
Definition: cc26x0_prcm.h:239
reg32_t JTAGCFG
JTAG config.
Definition: cc26x0_prcm.h:129
reg32_t RAMHWOPT
undocumented
Definition: cc26x0_prcm.h:281
reg32_t GPTCLKGR
GPT clock gate for run mode.
Definition: cc26x0_prcm.h:225
reg32_t GPTCLKDIV
GPT scalar.
Definition: cc26x0_prcm.h:244
reg32_t PDCTL0PERIPH
PERIPH power domain control.
Definition: cc26x0_prcm.h:256
reg32_t SECDMACLKGR
TRNG, CRYPTO, and UDMA clock gate for run mode.
Definition: cc26x0_prcm.h:219
reg32_t RFCCLKG
RFC clock gate.
Definition: cc26x0_prcm.h:216
reg32_t JTAGUSERCODE
JTAG USERCODE.
Definition: cc26x0_prcm.h:130
reg32_t AUXCFG
AUX config.
Definition: cc26x0_prcm.h:117
reg32_t PDSTAT0PERIPH
PERIPH power domain status.
Definition: cc26x0_prcm.h:261
reg32_t MCUCFG
MCU config.
Definition: cc26x0_prcm.h:116
reg32_t PDCTL1CPU
CPU power domain control.
Definition: cc26x0_prcm.h:265
reg32_t AMPCOMPCTL
amplitude compensation control
Definition: cc26x0_prcm.h:34
reg32_t XOSCHFCTL
XOSCHF control.
Definition: cc26x0_prcm.h:41
reg32_t ANABYPASSVAL1
analog bypass values 1
Definition: cc26x0_prcm.h:37
reg32_t RECHARGECFG
recharge controller config
Definition: cc26x0_prcm.h:125
reg32_t PDCTL0RFC
RFC power domain control.
Definition: cc26x0_prcm.h:254
reg32_t PDSTAT1VIMS
VIMS power domain status.
Definition: cc26x0_prcm.h:273
DDI_0_OSC registers.
Definition: cc26x0_prcm.h:30
reg32_t GPIOCLKGDS
GPIO clock gate for deep sleep mode.
Definition: cc26x0_prcm.h:224
reg32_t I2SBCLKDIV
BCLK division ratio.
Definition: cc26x0_prcm.h:247
reg32_t SSICLKGDS
SSI clock gate for deep sleep mode.
Definition: cc26x0_prcm.h:236
reg32_t GPIOCLKGR
GPIO clock gate for run mode.
Definition: cc26x0_prcm.h:222
reg32_t SECDMACLKGS
TRNG, CRYPTO, and UDMA clock gate for sleep mode.
Definition: cc26x0_prcm.h:220
reg32_t PDCTL1VIMS
VIMS power domain control.
Definition: cc26x0_prcm.h:267
reg32_t VDCTL
MCU voltage domain control.
Definition: cc26x0_prcm.h:213
reg32_t RFCMODESEL
selected RFC mode
Definition: cc26x0_prcm.h:275
reg32_t SSICLKGS
SSI clock gate for sleep mode.
Definition: cc26x0_prcm.h:235
reg32_t CPUCLKDIV
CPU clock division factor.
Definition: cc26x0_prcm.h:241
AON_SYSCTL registers.
Definition: cc26x0_prcm.h:95
reg32_t STAT0
status 0
Definition: cc26x0_prcm.h:44
reg32_t PDSTAT0
power domain status
Definition: cc26x0_prcm.h:258
reg32_t PDSTAT1CPU
CPU power domain status.
Definition: cc26x0_prcm.h:272
reg32_t UARTCLKGDS
UART clock gate for deep sleep mode.
Definition: cc26x0_prcm.h:233
reg32_t __reserved3
meh
Definition: cc26x0_prcm.h:127
reg32_t SSICLKGR
SSI clock gate for run mode.
Definition: cc26x0_prcm.h:234
reg32_t RCOSCHFCTL
RCOSCHF control.
Definition: cc26x0_prcm.h:43
CC26x0 MCU interrupt definitions.
reg32_t CLKLOADCTL
clock load control
Definition: cc26x0_prcm.h:215
reg32_t __reserved9
power domain control
Definition: cc26x0_prcm.h:264
reg32_t __reserved13
meh
Definition: cc26x0_prcm.h:278
reg32_t RECHARGESTAT
recharge controller status
Definition: cc26x0_prcm.h:126
reg32_t I2CCLKGR
I2C clock gate for run mode.
Definition: cc26x0_prcm.h:228
reg32_t UARTCLKGS
UART clock gate for sleep mode.
Definition: cc26x0_prcm.h:232
reg32_t PDSTAT0RFC
RFC power domain status.
Definition: cc26x0_prcm.h:259
reg32_t SLEEPCTL
sleep mode
Definition: cc26x0_prcm.h:98
reg32_t ADCDOUBLERNANOAMPCTL
ADC doubler nanoamp control.
Definition: cc26x0_prcm.h:40
reg32_t I2SCLKGR
I2S clock gate for run mode.
Definition: cc26x0_prcm.h:237
reg32_t AUXCLK
AUX clock management.
Definition: cc26x0_prcm.h:115
reg32_t GPTCLKGDS
GPT clock gate for deep sleep mode.
Definition: cc26x0_prcm.h:227
reg32_t VIMSCLKG
VIMS clock gate.
Definition: cc26x0_prcm.h:217
reg32_t I2CCLKGS
I2C clock gate for sleep mode.
Definition: cc26x0_prcm.h:229