cc26x0_gpt.h
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1 /*
2  * Copyright (C) 2016 Leon George
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef CC26X0_GPT_H
20 #define CC26X0_GPT_H
21 
22 #include "cc26x0.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
31 typedef struct {
32  reg32_t CFG;
33  reg32_t TAMR;
34  reg32_t TBMR;
35  reg32_t CTL;
36  reg32_t SYNC;
37  reg32_t __reserved1;
38  reg32_t IMR;
39  reg32_t RIS;
40  reg32_t MIS;
41  reg32_t ICLR;
42  reg32_t TAILR;
43  reg32_t TBILR;
44  reg32_t TAMATCHR;
45  reg32_t TBMATCHR;
46  reg32_t TAPR;
47  reg32_t TBPR;
48  reg32_t TAPMR;
49  reg32_t TBPMR;
50  reg32_t TAR;
51  reg32_t TBR;
52  reg32_t TAV;
53  reg32_t TBV;
54  reg32_t RTCPD;
55  reg32_t TAPS;
56  reg32_t TBPS;
57  reg32_t TAPV;
58  reg32_t TBPV;
59  reg32_t DMAEV;
60  reg32_t __reserved2[976];
61  reg32_t VERSION;
62  reg32_t ANDCCP;
63 } gpt_reg_t;
64 
69 #define GPT0_BASE (0x40010000)
70 #define GPT1_BASE (0x40011000)
71 #define GPT2_BASE (0x40012000)
72 #define GPT3_BASE (0x40013000)
79 #define GPT0 ((gpt_reg_t *) (GPT0_BASE))
80 #define GPT1 ((gpt_reg_t *) (GPT1_BASE))
81 #define GPT2 ((gpt_reg_t *) (GPT2_BASE))
82 #define GPT3 ((gpt_reg_t *) (GPT3_BASE))
83 
89 #define GPT_CFG_32T 0
90 #define GPT_CFG_32RTC 1
91 #define GPT_CFG_16T 4
92 
93 #define GPT_TXMR_TXMR_ONE_SHOT 0x00000001
94 #define GPT_TXMR_TXMR_PERIODIC 0x00000002
95 #define GPT_TXMR_TXMR_CAPTURE 0x00000003
96 #define GPT_TXMR_TXCM_EDGECNT 0x00000000
97 #define GPT_TXMR_TXCM_EDGETIME 0x00000004
98 #define GPT_TXMR_TXAMS_CAPTCOMP 0x00000000
99 #define GPT_TXMR_TXAMS_PWM 0x00000008
100 #define GPT_TXMR_TXCDIR_DOWN 0x00000000
101 #define GPT_TXMR_TXCDIR_UP 0x00000010 /* starts from 0 */
102 #define GPT_TXMR_TXMIE 0x00000020 /* match interrupt */
103 #define GPT_TXMR_TXWOT 0x00000040 /* wait on trigger from daisy */
104 #define GPT_TXMR_TXSNAPS 0x00000080
105 #define GPT_TXMR_TXILD_CLOCK 0x00000000 /* interrupt loac: update TXPR or TXR */
106 #define GPT_TXMR_TXILD_TIMEOUT 0x00000100
107 #define GPT_TXMR_TXPWMIE 0x00000200
108 #define GPT_TXMR_TXMRSU 0x00000400
109 #define GPT_TXMR_TXPLO 0x00000800
110 #define GPT_TXMR_TXCIN 0x00001000
111 #define GPT_TXMR_TCACT_DIS 0x00000000
112 #define GPT_TXMR_TCACT_TGL_TO 0x00002000
113 #define GPT_TXMR_TCACT_CLR_TO 0x00004000
114 #define GPT_TXMR_TCACT_SET_TO 0x00006000
115 #define GPT_TXMR_TCACT_SET_NOW_TGL_TO 0x00008000
116 #define GPT_TXMR_TCACT_CLR_NOW_TGL_TO 0x0000a000
117 #define GPT_TXMR_TCACT_SET_NOW_CLR_TO 0x0000c000
118 #define GPT_TXMR_TCACT_CLR_NOW_SET_TO 0x0000e000
119 
120 #define GPT_CTL_TAEN 0x00000001
121 #define GPT_CTL_TASTALL 0x00000002
122 #define GPT_CTL_TAEVENT_POS 0x00000000
123 #define GPT_CTL_TAEVENT_NEG 0x00000004
124 #define GPT_CTL_TAEVENT_BOTH 0x0000000c
125 #define GPT_CTL_RTCEN 0x00000010
126 #define GPT_CTL_TAPWML_INV 0x00000040
127 #define GPT_CTL_TBEN 0x00000100 /* still need capture CFG */
128 #define GPT_CTL_TBSTALL 0x00000200
129 #define GPT_CTL_TBEVENT_POS 0x00000000
130 #define GPT_CTL_TBEVENT_NEG 0x00000400
131 #define GPT_CTL_TBEVENT_BOTH 0x00000c00
132 #define GPT_CTL_TBPWML_INV 0x00004000
133 
134 #define GPT_SYNC_SYNC1_A 0x00000001
135 #define GPT_SYNC_SYNC1_B 0x00000002
136 #define GPT_SYNC_SYNC2_A 0x00000004
137 #define GPT_SYNC_SYNC2_B 0x00000008
138 #define GPT_SYNC_SYNC3_A 0x00000010
139 #define GPT_SYNC_SYNC3_B 0x00000020
140 #define GPT_SYNC_SYNC4_A 0x00000040
141 #define GPT_SYNC_SYNC4_B 0x00000080
142 
143 #define GPT_IMR_TATOIM 0x00000001
144 #define GPT_IMR_CAMIM 0x00000002
145 #define GPT_IMR_CAEIM 0x00000004
146 #define GPT_IMR_RTCIM 0x00000008
147 #define GPT_IMR_TAMIM 0x00000010
148 #define GPT_IMR_DMAAIM 0x00000020
149 #define GPT_IMR_TBTOIM 0x00000100
150 #define GPT_IMR_CBMIM 0x00000200
151 #define GPT_IMR_CBEIM 0x00000400
152 #define GPT_IMR_TBMIM 0x00000800
153 #define GPT_IMR_DMABIM 0x00002000
154 #define GPT_IMR_WUMIS 0x00010000
155 
156 #define GPT_RIS_TATORIS 0x00000001
157 #define GPT_RIS_CAMRIS 0x00000002
158 #define GPT_RIS_CAERIS 0x00000004
159 #define GPT_RIS_RTCRIS 0x00000008
160 #define GPT_RIS_TAMRIS 0x00000010
161 #define GPT_RIS_TBTORIS 0x00000100
162 #define GPT_RIS_CBMRIS 0x00000200
163 #define GPT_RIS_CBERIS 0x00000400
164 #define GPT_RIS_TBMRIS 0x00000800
165 #define GPT_RIS_DMARIS 0x00002000
166 #define GPT_RIS_WURIS 0x00010000
167 
168 #define GPT_MIS_TATOMIS 0x00000001
169 #define GPT_MIS_CAMMIS 0x00000002
170 #define GPT_MIS_CAEMIS 0x00000004
171 #define GPT_MIS_RTCMIS 0x00000008
172 #define GPT_MIS_TAMMIS 0x00000010
173 #define GPT_MIS_TBTOMIS 0x00000100
174 #define GPT_MIS_CBMMIS 0x00000200
175 #define GPT_MIS_CBEMIS 0x00000400
176 #define GPT_MIS_TBMMIS 0x00000800
177 #define GPT_MIS_DMAMIS 0x00002000
178 #define GPT_MIS_WUMIS 0x00010000
179 
180 #define GPT_ICLR_TATOCINT 0x00000001
181 #define GPT_ICLR_CAMCINT 0x00000002
182 #define GPT_ICLR_CAECINT 0x00000004
183 #define GPT_ICLR_RTCCINT 0x00000008
184 #define GPT_ICLR_TAMCINT 0x00000010
185 #define GPT_ICLR_TBTOCINT 0x00000100
186 #define GPT_ICLR_CBMCINT 0x00000200
187 #define GPT_ICLR_CBECINT 0x00000400
188 #define GPT_ICLR_TBMCINT 0x00000800
189 #define GPT_ICLR_DMACINT 0x00002000
190 #define GPT_ICLR_WUCINT 0x00010000
191 
192 #define GPT_DMAEV_TATODMAEN 0x00000001
193 #define GPT_DMAEV_CAMDMAEN 0x00000002
194 #define GPT_DMAEV_CAEDMAEN 0x00000004
195 #define GPT_DMAEV_RTCDMAEN 0x00000008
196 #define GPT_DMAEV_TAMDMAEN 0x00000010
197 #define GPT_DMAEV_TBTODMAEN 0x00000100
198 #define GPT_DMAEV_CBMDMAEN 0x00000200
199 #define GPT_DMAEV_CBEDMAEN 0x00000400
200 #define GPT_DMAEV_TBMDMAEN 0x00000800
201 
203 #define GPT_NUMOF 4
204 #define NUM_CHANNELS_PER_GPT 1
206 #ifdef __cplusplus
207 }
208 #endif
209 
210 #endif /* CC26X0_GPT_H */
211 
reg32_t RTCPD
config
Definition: cc26x0_gpt.h:54
reg32_t TBV
timer B value
Definition: cc26x0_gpt.h:53
reg32_t TBPMR
timer B pre-scale match register
Definition: cc26x0_gpt.h:49
reg32_t TAILR
timer A interval load register
Definition: cc26x0_gpt.h:42
reg32_t DMAEV
config
Definition: cc26x0_gpt.h:59
reg32_t CFG
config
Definition: cc26x0_gpt.h:32
reg32_t TAMATCHR
timer A match register
Definition: cc26x0_gpt.h:44
reg32_t ANDCCP
config
Definition: cc26x0_gpt.h:62
reg32_t TAPS
config
Definition: cc26x0_gpt.h:55
reg32_t TBMR
timer B mode
Definition: cc26x0_gpt.h:34
reg32_t VERSION
config
Definition: cc26x0_gpt.h:61
GPT registers.
Definition: cc26x0_gpt.h:31
reg32_t TBPR
timer B pre-scale
Definition: cc26x0_gpt.h:47
reg32_t IMR
interrupt mask register
Definition: cc26x0_gpt.h:38
reg32_t TAV
timer A value
Definition: cc26x0_gpt.h:52
reg32_t ICLR
interrupt clear
Definition: cc26x0_gpt.h:41
reg32_t TBR
timer B register
Definition: cc26x0_gpt.h:51
reg32_t TBPS
config
Definition: cc26x0_gpt.h:56
reg32_t TAR
timer A register
Definition: cc26x0_gpt.h:50
reg32_t TBMATCHR
timer B match register
Definition: cc26x0_gpt.h:45
reg32_t __reserved1
unused
Definition: cc26x0_gpt.h:37
reg32_t SYNC
sync timers
Definition: cc26x0_gpt.h:36
reg32_t RIS
raw interrupt status
Definition: cc26x0_gpt.h:39
reg32_t TAPV
config
Definition: cc26x0_gpt.h:57
CC26x0 MCU interrupt definitions.
reg32_t TAPR
timer A pre-scale
Definition: cc26x0_gpt.h:46
reg32_t TBILR
timer B interval load register
Definition: cc26x0_gpt.h:43
reg32_t TBPV
config
Definition: cc26x0_gpt.h:58
reg32_t TAMR
timer A mode
Definition: cc26x0_gpt.h:33
reg32_t TAPMR
timer A pre-scale match register
Definition: cc26x0_gpt.h:48
reg32_t CTL
control
Definition: cc26x0_gpt.h:35
reg32_t MIS
masked interrupt status
Definition: cc26x0_gpt.h:40