cc26x0_fcfg.h
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1 /*
2  * Copyright (C) 2016 Leon George
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
16 #ifndef CC26X0_FCFG_H
17 #define CC26X0_FCFG_H
18 
19 #include <cc26x0.h>
20 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
28 #define FCFG_BASE 0x50001000
30 
31 
34 typedef struct {
35  uint8_t __reserved1[0xA0];
36  /* TODO does it pad here? */
37  reg32_t MISC_CONF_1;
38  reg32_t __reserved2[8];
57  reg32_t __reserved3[3];
58  reg32_t SHDW_DIE_ID_0;
59  reg32_t SHDW_DIE_ID_1;
60  reg32_t SHDW_DIE_ID_2;
61  reg32_t SHDW_DIE_ID_3;
62  reg32_t __reserved4[4];
64  reg32_t SHDW_ANA_TRIM;
65  reg32_t __reserved5[9];
66  reg32_t FLASH_NUMBER;
67  reg32_t FLASH_COORDINATE;
68  reg32_t FLASH_E_P;
69  reg32_t FLASH_C_E_P_R;
70  reg32_t FLASH_P_R_PV;
71  reg32_t FLASH_EH_SEQ;
72  reg32_t FLASH_VHV_E;
73  reg32_t FLASH_PP;
74  reg32_t FLASH_PROG_EP;
75  reg32_t FLASH_ERA_PW;
76  reg32_t FLASH_VHV;
77  reg32_t FLASH_VHV_PV;
78  reg32_t FLASH_V;
79  reg32_t __reserved6[0x3E];
80  reg32_t USER_ID;
81  reg32_t __reserved7[6];
82  reg32_t FLASH_OTP_DATA3;
83  reg32_t ANA2_TRIM;
84  reg32_t LDO_TRIM;
85  reg32_t __reserved8[0xB];
86  reg32_t MAC_BLE_0;
87  reg32_t MAC_BLE_1;
88  reg32_t MAC_15_4_0;
89  reg32_t MAC_15_4_1;
90  reg32_t __reserved9[4];
91  reg32_t FLASH_OTP_DATA4;
92  reg32_t MISC_TRIM;
94  reg32_t __reserved10;
96  reg32_t FCFG1_REVISION;
97  reg32_t MISC_OTP_DATA;
98  reg32_t __reserved11[8];
99  reg32_t IOCONF;
100  reg32_t __reserved12;
101  reg32_t CONFIG_IF_ADC;
102  reg32_t CONFIG_OSC_TOP;
104  reg32_t CONFIG_SYNTH;
107  reg32_t __reserved13;
110  reg32_t AMPCOMP_TH1;
111  reg32_t AMPCOMP_TH2;
112  reg32_t AMPCOMP_CTRL1;
114  reg32_t CONFIG_MISC_ADC;
115  reg32_t __reserved14;
116  reg32_t VOLT_TRIM;
117  reg32_t OSC_CONF;
118  reg32_t __reserved15;
119  reg32_t CAP_TRIM;
120  reg32_t MISC_OTP_DATA_1;
121  reg32_t PWD_CURR_20C;
122  reg32_t PWD_CURR_35C;
123  reg32_t PWD_CURR_50C;
124  reg32_t PWD_CURR_65C;
125  reg32_t PWD_CURR_80C;
126  reg32_t PWD_CURR_95C;
127  reg32_t PWD_CURR_110C;
128  reg32_t PWD_CURR_125C;
129 } fcfg_regs_t;
130 
131 #define FCFG ((fcfg_regs_t *) (FCFG_BASE))
133 #ifdef __cplusplus
134 } /* end extern "C" */
135 #endif
136 
137 #endif /* CC26X0_FCFG_H */
138 
reg32_t CONFIG_OSC_TOP
config of OSC
Definition: cc26x0_fcfg.h:102
reg32_t CONFIG_RF_FRONTEND_DIV12
config of RF frontend in divide-by-12 mode
Definition: cc26x0_fcfg.h:42
reg32_t CONFIG_SYNTH_DIV12
config of synthesizer in divide-by-12-mode
Definition: cc26x0_fcfg.h:48
reg32_t ANABYPASS_VALUE2
analog bypass value for OSC
Definition: cc26x0_fcfg.h:113
reg32_t SHDW_DIE_ID_2
shadow of JTAG_TAP::EFUSE::DIE_ID_2.
Definition: cc26x0_fcfg.h:60
reg32_t AMPCOMP_TH2
amplitude compensation threshold 2
Definition: cc26x0_fcfg.h:111
reg32_t AMPCOMP_CTRL1
amplitude compensation control
Definition: cc26x0_fcfg.h:112
reg32_t CONFIG_RF_FRONTEND_DIV5
config of RF frontend in divide-by-5 mode
Definition: cc26x0_fcfg.h:39
reg32_t SHDW_DIE_ID_1
shadow of JTAG_TAP::EFUSE::DIE_ID_1.
Definition: cc26x0_fcfg.h:59
reg32_t CONFIG_SYNTH
config of synthesizer in dividy-by-2-mode
Definition: cc26x0_fcfg.h:104
reg32_t __reserved14
meh
Definition: cc26x0_fcfg.h:115
reg32_t PWD_CURR_95C
power down current control 95C
Definition: cc26x0_fcfg.h:126
reg32_t LDO_TRIM
LDO trim.
Definition: cc26x0_fcfg.h:84
reg32_t SHDW_OSC_BIAS_LDO_TRIM
shadow of JTAG_TAP::EFUSE::BIAS_LDO_TIM.
Definition: cc26x0_fcfg.h:63
reg32_t FLASH_E_P
flash erase and program setup time
Definition: cc26x0_fcfg.h:68
reg32_t IOCONF
IO config.
Definition: cc26x0_fcfg.h:99
reg32_t MISC_OTP_DATA_1
misc OSC control
Definition: cc26x0_fcfg.h:120
reg32_t MAC_BLE_0
MAC BLE address 0.
Definition: cc26x0_fcfg.h:86
reg32_t MISC_OTP_DATA
misc OTP data
Definition: cc26x0_fcfg.h:97
reg32_t CONFIG_IF_ADC
config of IF_ADC
Definition: cc26x0_fcfg.h:101
reg32_t USER_ID
user identification
Definition: cc26x0_fcfg.h:80
reg32_t FLASH_ERA_PW
flash erase pulse width
Definition: cc26x0_fcfg.h:75
reg32_t CAP_TRIM
capacitor trim (it says 'capasitor' in the manual - if you know what that is ;-)
Definition: cc26x0_fcfg.h:119
reg32_t PWD_CURR_20C
power down current control 20C
Definition: cc26x0_fcfg.h:121
reg32_t SOC_ADC_OFFSET_INT
AUX_ADC temperature offsets in absolute reference mode.
Definition: cc26x0_fcfg.h:108
reg32_t CONFIG_RF_FRONTEND_DIV30
config of RF frontend in divide-by-30 mode
Definition: cc26x0_fcfg.h:44
reg32_t PWD_CURR_65C
power down current control 65C
Definition: cc26x0_fcfg.h:124
reg32_t SOC_ADC_ABS_GAIN
AUX_ADC gain in absolute reference mode.
Definition: cc26x0_fcfg.h:105
reg32_t FLASH_OTP_DATA3
flash OTP data 3
Definition: cc26x0_fcfg.h:82
reg32_t FLASH_OTP_DATA4
flash OTP data 4
Definition: cc26x0_fcfg.h:91
reg32_t CONFIG_MISC_ADC_DIV30
config of IFADC in divide-by-30-mode
Definition: cc26x0_fcfg.h:56
reg32_t FLASH_VHV_PV
flash VHV program verify
Definition: cc26x0_fcfg.h:77
reg32_t MISC_TRIM
misc trim parameters
Definition: cc26x0_fcfg.h:92
reg32_t FCFG1_REVISION
FCFG1 revision.
Definition: cc26x0_fcfg.h:96
reg32_t FLASH_NUMBER
number of manufactoring lot that produced this unit
Definition: cc26x0_fcfg.h:66
reg32_t CONFIG_RF_FRONTEND_DIV10
config of RF frontend in divide-by-10 mode
Definition: cc26x0_fcfg.h:41
reg32_t MAC_15_4_1
MAC IEEE 820.15.4 address 1.
Definition: cc26x0_fcfg.h:89
reg32_t ANA2_TRIM
misc analog trim
Definition: cc26x0_fcfg.h:83
reg32_t PWD_CURR_80C
power down current control 80C
Definition: cc26x0_fcfg.h:125
reg32_t CONFIG_RF_FRONTEND
config of RF frontend in dividy-by-2-mode
Definition: cc26x0_fcfg.h:103
reg32_t OSC_CONF
OSC configuration.
Definition: cc26x0_fcfg.h:117
reg32_t FLASH_VHV
flash VHV
Definition: cc26x0_fcfg.h:76
reg32_t VOLT_TRIM
voltage trim
Definition: cc26x0_fcfg.h:116
reg32_t PWD_CURR_125C
power down current control 125C
Definition: cc26x0_fcfg.h:128
reg32_t CONFIG_SYNTH_DIV10
config of synthesizer in divide-by-10-mode
Definition: cc26x0_fcfg.h:47
reg32_t FLASH_VHV_E
flash VHV erase
Definition: cc26x0_fcfg.h:72
reg32_t SOC_ADC_REL_GAIN
AUX_ADC gain in relative reference mode.
Definition: cc26x0_fcfg.h:106
reg32_t CONFIG_RF_FRONTEND_DIV6
config of RF frontend in divide-by-6 mode
Definition: cc26x0_fcfg.h:40
reg32_t SHDW_ANA_TRIM
shadow of JTAG_TAP::EFUSE::ANA_TIM.
Definition: cc26x0_fcfg.h:64
reg32_t SHDW_DIE_ID_0
shadow of JTAG_TAP::EFUSE::DIE_ID_0.
Definition: cc26x0_fcfg.h:58
reg32_t AMPCOMP_TH1
amplitude compensation threshold 1
Definition: cc26x0_fcfg.h:110
reg32_t __reserved12
meh
Definition: cc26x0_fcfg.h:100
reg32_t CONFIG_SYNTH_DIV15
config of synthesizer in divide-by-15-mode
Definition: cc26x0_fcfg.h:49
reg32_t CONFIG_MISC_ADC
config of IFADC in divide-by-2-mode
Definition: cc26x0_fcfg.h:114
reg32_t CONFIG_SYNTH_DIV5
config of synthesizer in divide-by-5-mode
Definition: cc26x0_fcfg.h:45
reg32_t __reserved15
meh
Definition: cc26x0_fcfg.h:118
reg32_t ICEPICK_DEVICE_ID
IcePick device identification.
Definition: cc26x0_fcfg.h:95
reg32_t CONFIG_MISC_ADC_DIV6
config of IFADC in divide-by-6-mode
Definition: cc26x0_fcfg.h:52
reg32_t PWD_CURR_110C
power down current control 110C
Definition: cc26x0_fcfg.h:127
reg32_t CONFIG_MISC_ADC_DIV15
config of IFADC in divide-by-15-mode
Definition: cc26x0_fcfg.h:55
reg32_t MAC_15_4_0
MAC IEEE 820.15.4 address 0.
Definition: cc26x0_fcfg.h:88
reg32_t PWD_CURR_35C
power down current control 35C
Definition: cc26x0_fcfg.h:122
reg32_t FLASH_PP
flash program pulse
Definition: cc26x0_fcfg.h:73
reg32_t SOC_ADC_REF_TRIM_AND_OFFSET_EXT
AUX_ADC reference trim and offset of external reference mode.
Definition: cc26x0_fcfg.h:109
reg32_t SHDW_DIE_ID_3
shadow of JTAG_TAP::EFUSE::DIE_ID_3.
Definition: cc26x0_fcfg.h:61
reg32_t CONFIG_SYNTH_DIV6
config of synthesizer in divide-by-5-mode
Definition: cc26x0_fcfg.h:46
reg32_t FLASH_P_R_PV
flash program, read, and program verify
Definition: cc26x0_fcfg.h:70
reg32_t FLASH_COORDINATE
X and Y coordinates of this unit on the wafer.
Definition: cc26x0_fcfg.h:67
reg32_t PWD_CURR_50C
power down current control 50C
Definition: cc26x0_fcfg.h:123
reg32_t MISC_CONF_1
misc config
Definition: cc26x0_fcfg.h:37
reg32_t FLASH_V
flash voltages
Definition: cc26x0_fcfg.h:78
reg32_t RCOSC_HF_TEMPCOMP
RFOSC HF temperature compensation.
Definition: cc26x0_fcfg.h:93
reg32_t MAC_BLE_1
MAC BLE address 1.
Definition: cc26x0_fcfg.h:87
CC26x0 MCU interrupt definitions.
reg32_t CONFIG_MISC_ADC_DIV12
config of IFADC in divide-by-12-mode
Definition: cc26x0_fcfg.h:54
reg32_t FLASH_C_E_P_R
flash compaction, execute, program, and read
Definition: cc26x0_fcfg.h:69
reg32_t CONFIG_MISC_ADC_DIV10
config of IFADC in divide-by-10-mode
Definition: cc26x0_fcfg.h:53
reg32_t __reserved10
meh
Definition: cc26x0_fcfg.h:94
reg32_t CONFIG_MISC_ADC_DIV5
config of IFADC in divide-by-5-mode
Definition: cc26x0_fcfg.h:51
reg32_t __reserved13
meh
Definition: cc26x0_fcfg.h:107
reg32_t CONFIG_RF_FRONTEND_DIV15
config of RF frontend in divide-by-15 mode
Definition: cc26x0_fcfg.h:43
FCFG registers.
Definition: cc26x0_fcfg.h:34
reg32_t FLASH_PROG_EP
flash program and erase pulse
Definition: cc26x0_fcfg.h:74
reg32_t CONFIG_SYNTH_DIV30
config of synthesizer in divide-by-30-mode
Definition: cc26x0_fcfg.h:50
reg32_t FLASH_EH_SEQ
flash erase hold and sequence
Definition: cc26x0_fcfg.h:71