cc26x0.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2016 Leon George
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef CC26X0_H
20 #define CC26X0_H
21 
22 #include <stdint.h>
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 typedef volatile uint8_t reg8_t;
29 typedef volatile uint32_t reg32_t;
30 
33 
35 typedef enum IRQn
36 {
37  /****** Cortex-M3 Processor Exceptions Numbers ****************************/
42  BusFault_IRQn = -11,
44  SVCall_IRQn = - 5,
46  PendSV_IRQn = - 2,
47  SysTick_IRQn = - 1,
49  /****** CC26x0 specific Interrupt Numbers *********************************/
51  I2C_IRQN = 1,
53  SPIS_IRQN = 3,
55  UART0_IRQN = 5,
57  SSI0_IRQN = 7,
58  SSI1_IRQN = 8,
60  RF_HW_IRQN = 10,
62  I2S_IRQN = 12,
73  CRYPTO_IRQN = 23,
74  UDMA_IRQN = 24,
77  SW0_IRQN = 27,
80  PROG_IRQN = 30,
82  AUX_ADC_IRQN = 32,
83  TRNG_IRQN = 33,
86 } IRQn_Type;
87 
92 #define __MPU_PRESENT 1
93 #define __NVIC_PRIO_BITS 3
94 #define __Vendor_SysTickConfig 0
96 #define RCOSC48M_FREQ 48000000
97 #define RCOSC24M_FREQ 24000000
102 #include <core_cm3.h>
103 
108 #define FLASH_BASE 0x00000000
110 
111 #ifdef __cplusplus
112 }
113 #endif
114 
115 #endif /* CC26X0_H */
116 
11 Cortex-M3 SV Call Interrupt
Definition: cc26x0.h:44
38 Timer 3 subtimer B
Definition: cc26x0.h:72
17 I2C
Definition: cc26x0.h:51
27 RF Core Command Acknowledge
Definition: cc26x0.h:61
enum IRQn IRQn_Type
Interrupt Number Definition.
36 Timer 2 subtimer B
Definition: cc26x0.h:70
34 Timer 1 subtimer B
Definition: cc26x0.h:68
41 uDMA Error
Definition: cc26x0.h:75
6 Cortex-M3 Usage Fault Interrupt
Definition: cc26x0.h:43
32 Timer 0 subtimer B
Definition: cc26x0.h:66
31 Timer 0 subtimer A
Definition: cc26x0.h:65
30 Watchdog timer
Definition: cc26x0.h:64
37 Timer 3 subtimer A
Definition: cc26x0.h:71
20 AON RTC
Definition: cc26x0.h:54
29 Sensor Controller software event 1, through AON domain
Definition: cc26x0.h:63
18 RF Command and Packet Engine 1
Definition: cc26x0.h:52
15 Cortex-M3 System Tick Interrupt
Definition: cc26x0.h:47
26 RF Core Hardware
Definition: cc26x0.h:60
43 Software Event 0
Definition: cc26x0.h:77
39 Crypto Core Result available
Definition: cc26x0.h:73
46 Dynamic Programmable interrupt (default source: PRCM)
Definition: cc26x0.h:80
14 Cortex-M3 Pend SV Interrupt
Definition: cc26x0.h:46
5 Cortex-M3 Bus Fault Interrupt
Definition: cc26x0.h:42
4 Cortex-M3 Memory Management Interrupt
Definition: cc26x0.h:41
19 AON SpiSplave Rx, Tx and CS
Definition: cc26x0.h:53
16 AON edge detect
Definition: cc26x0.h:50
Number of peripheral IDs.
Definition: cc26x0.h:85
49 TRNG event
Definition: cc26x0.h:83
48 AUX ADC IRQ
Definition: cc26x0.h:82
47 AUX Comparator A
Definition: cc26x0.h:81
28 I2S
Definition: cc26x0.h:62
33 Timer 1 subtimer A
Definition: cc26x0.h:67
12 Cortex-M3 Debug Monitor Interrupt
Definition: cc26x0.h:45
40 uDMA Software
Definition: cc26x0.h:74
44 AUX combined event, directly to MCU domain
Definition: cc26x0.h:78
22 Sensor Controller software event 0, through AON domain
Definition: cc26x0.h:56
25 RF Command and Packet Engine 0
Definition: cc26x0.h:59
IRQn
Interrupt Number Definition.
Definition: cc2538.h:33
24 SSI1 Rx and Tx
Definition: cc26x0.h:58
23 SSI0 Rx and Tx
Definition: cc26x0.h:57
3 Cortex-M3 Hard Fault Interrupt
Definition: cc26x0.h:40
35 Timer 2 subtimer A
Definition: cc26x0.h:69
42 Flash controller
Definition: cc26x0.h:76
45 AON programmable 0
Definition: cc26x0.h:79
1 Reset Handler
Definition: cc26x0.h:38
21 UART0 Rx and Tx
Definition: cc26x0.h:55
2 Non Maskable Interrupt
Definition: cc26x0.h:39