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CC26x0 MCU interrupt definitions. More...

Detailed Description

Author
Leon M. George leon@.nosp@m.geor.nosp@m.gemai.nosp@m.l.eu

Definition in file cc26x0.h.

#include <stdint.h>
#include <core_cm3.h>
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Go to the source code of this file.

Macros

#define FLASH_BASE   0x00000000
 CMSIS includes. More...
 
#define __MPU_PRESENT   1
 Configuration of the Cortex-M3 processor and core peripherals. More...
 
#define __NVIC_PRIO_BITS   3
 CC26x0 offers priority levels from 0..7.
 
#define __Vendor_SysTickConfig   0
 Set to 1 if different SysTick config is used.
 
#define RCOSC48M_FREQ   48000000
 48 MHz
 
#define RCOSC24M_FREQ   24000000
 24 MHz
 
enum  IRQn {
  ResetHandler_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = - 5, DebugMonitor_IRQn = - 4,
  PendSV_IRQn = - 2, SysTick_IRQn = - 1, GPIO_PORT_A_IRQn = 0, GPIO_PORT_B_IRQn = 1,
  GPIO_PORT_C_IRQn = 2, GPIO_PORT_D_IRQn = 3, UART0_IRQn = 5, UART1_IRQn = 6,
  SSI0_IRQn = 7, I2C_IRQn = 8, ADC_IRQn = 14, WDT_IRQn = 18,
  GPTIMER_0A_IRQn = 19, GPTIMER_0B_IRQn = 20, GPTIMER_1A_IRQn = 21, GPTIMER_1B_IRQn = 22,
  GPTIMER_2A_IRQn = 23, GPTIMER_2B_IRQn = 24, ADC_CMP_IRQn = 25, RF_RXTX_ALT_IRQn = 26,
  RF_ERR_ALT_IRQn = 27, SYS_CTRL_IRQn = 28, FLASH_CTRL_IRQn = 29, AES_ALT_IRQn = 30,
  PKA_ALT_IRQn = 31, SM_TIMER_ALT_IRQn = 32, MAC_TIMER_ALT_IRQn = 33, SSI1_IRQn = 34,
  GPTIMER_3A_IRQn = 35, GPTIMER_3B_IRQn = 36, UDMA_IRQn = 46, UDMA_ERR_IRQn = 47,
  USB_IRQn = 140, RF_RXTX_IRQn = 141, RF_ERR_IRQn = 142, AES_IRQn = 143,
  PKA_IRQn = 144, SM_TIMER_IRQn = 145, MACTIMER_IRQn = 146, PERIPH_COUNT_IRQn = (MACTIMER_IRQn + 1),
  ResetHandler_IRQn = -15, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12,
  BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = - 5, DebugMonitor_IRQn = - 4,
  PendSV_IRQn = - 2, SysTick_IRQn = - 1, EDGE_DETECT_IRQN = 0, I2C_IRQN = 1,
  RF_CPE1_IRQN = 2, SPIS_IRQN = 3, AON_RTC_IRQN = 4, UART0_IRQN = 5,
  AON_AUX_SWEV0_IRQN = 6, SSI0_IRQN = 7, SSI1_IRQN = 8, RF_CPE0_IRQN = 9,
  RF_HW_IRQN = 10, RF_CMD_ACK_IRQN = 11, I2S_IRQN = 12, AON_AUX_SWEV1_IRQN = 13,
  WATCHDOG_IRQN = 14, GPTIMER_0A_IRQN = 15, GPTIMER_0B_IRQN = 16, GPTIMER_1A_IRQN = 17,
  GPTIMER_1B_IRQN = 18, GPTIMER_2A_IRQN = 19, GPTIMER_2B_IRQN = 20, GPTIMER_3A_IRQN = 21,
  GPTIMER_3B_IRQN = 22, CRYPTO_IRQN = 23, UDMA_IRQN = 24, UDMA_ERR_IRQN = 25,
  FLASH_CTRL_IRQN = 26, SW0_IRQN = 27, AUX_COMBO_IRQN = 28, AON_PRG0_IRQN = 29,
  PROG_IRQN = 30, AUX_COMPA_IRQN = 31, AUX_ADC_IRQN = 32, TRNG_IRQN = 33,
  IRQN_COUNT = (TRNG_IRQN + 1)
}
 interrupt number definition More...
 
typedef volatile uint8_t reg8_t
 
typedef volatile uint32_t reg32_t
 
typedef enum IRQn IRQn_Type
 interrupt number definition