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1 /*
2  * Copyright (C) 2014 Loci Controls Inc.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
20 #ifndef CC2538_UART_H
21 #define CC2538_UART_H
23 #include "cc2538.h"
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
32 typedef struct {
38  union {
41  } cc2538_uart_dr;
43  cc2538_reg_t RESERVED1[4];
48  union {
50  struct {
58  cc2538_reg_t RESERVED1 : 24;
59  } FRbits;
60  } cc2538_uart_fr;
62  cc2538_reg_t RESERVED2;
70  union {
72  struct {
81  } LCRHbits;
82  } cc2538_uart_lcrh;
87  union {
89  struct {
104  } CTLbits;
105  } cc2538_uart_ctl;
110  union {
112  struct {
115  cc2538_reg_t RESERVED : 26;
116  } IFLSbits;
117  } cc2538_uart_ifls;
122  union {
124  struct {
133  cc2538_reg_t RESERVED2 : 1;
138  cc2538_reg_t RESERVED1 : 16;
139  } IMbits;
140  } cc2538_uart_im;
147  union {
149  struct {
164  } MISbits;
165  } cc2538_uart_mis;
169  cc2538_reg_t RESERVED3[17];
173  cc2538_reg_t RESERVED4[2];
176  cc2538_reg_t RESERVED5[965];
180  cc2538_reg_t RESERVED7[13];
181 } cc2538_uart_t;
183 #define UART0_BASEADDR (cc2538_uart_t *)(&UART0_DR)
184 #define UART1_BASEADDR (cc2538_uart_t *)(&UART1_DR)
186 #ifdef __cplusplus
187 } /* end extern "C" */
188 #endif
190 #endif /* CC2538_UART_H */
cc2538_reg_t LME1IM
LIN mode edge 1 interrupt mask.
Definition: cc2538_uart.h:136
cc2538_reg_t CTL
UART Control.
Definition: cc2538_uart.h:88
cc2538_reg_t RIS
UART Raw Interrupt Status.
Definition: cc2538_uart.h:142
cc2538_reg_t RTMIS
UART receive time-out masked interrupt status.
Definition: cc2538_uart.h:153
cc2538_reg_t RXIFLSEL
UART receive interrupt FIFO level select.
Definition: cc2538_uart.h:114
cc2538_reg_t SIRLP
UART SIR low-power mode.
Definition: cc2538_uart.h:92
cc2538_reg_t CTS
Clear to send (UART1 only)
Definition: cc2538_uart.h:51
cc2538_reg_t CTSEN
U1CTS Hardware flow control enable.
Definition: cc2538_uart.h:102
cc2538_reg_t IFLS
UART interrupt FIFO Level Select.
Definition: cc2538_uart.h:111
cc2538_reg_t RESERVED2
Reserved bits.
Definition: cc2538_uart.h:52
cc2538_reg_t FEMIS
UART framing error masked interrupt status.
Definition: cc2538_uart.h:154
cc2538_reg_t SIREN
UART SIR enable.
Definition: cc2538_uart.h:91
cc2538_reg_t EPS
UART even parity select.
Definition: cc2538_uart.h:75
cc2538_reg_t ICR
UART Interrupt Clear Register.
Definition: cc2538_uart.h:167
cc2538_reg_t FR
UART Flag Register.
Definition: cc2538_uart.h:49
cc2538_reg_t CC
UART Clock Configuration.
Definition: cc2538_uart.h:179
cc2538_reg_t LCTL
UART LIN Control.
Definition: cc2538_uart.h:170
cc2538_reg_t LSS
UART LIN Snap Shot.
Definition: cc2538_uart.h:171
cc2538_reg_t OEIM
UART overrun error interrupt mask.
Definition: cc2538_uart.h:132
cc2538_reg_t EOT
End of transmission.
Definition: cc2538_uart.h:94
cc2538_reg_t BEMIS
UART break error masked interrupt status.
Definition: cc2538_uart.h:156
cc2538_reg_t NINEBITMIS
9-bit mode masked interrupt status
Definition: cc2538_uart.h:159
cc2538_reg_t SPS
UART stick parity select.
Definition: cc2538_uart.h:79
cc2538_reg_t FEN
UART enable FIFOs.
Definition: cc2538_uart.h:77
cc2538_reg_t UARTEN
UART enable.
Definition: cc2538_uart.h:90
cc2538_reg_t RXIM
UART receive interrupt mask.
Definition: cc2538_uart.h:126
cc2538_reg_t RESERVED3
Reserved bits.
Definition: cc2538_uart.h:125
cc2538_reg_t LME5IM
LIN mode edge 5 interrupt mask.
Definition: cc2538_uart.h:137
cc2538_reg_t RESERVED8
Reserved bits.
Definition: cc2538_uart.h:150
cc2538_reg_t PEIM
UART parity error interrupt mask.
Definition: cc2538_uart.h:130
cc2538_reg_t TXFF
UART transmit FIFO full.
Definition: cc2538_uart.h:55
cc2538_reg_t RESERVED6
Reserved addresses.
Definition: cc2538_uart.h:178
cc2538_reg_t WLEN
UART word length.
Definition: cc2538_uart.h:78
cc2538_reg_t RXFE
UART receive FIFO empty.
Definition: cc2538_uart.h:54
cc2538_reg_t LME1MIS
LIN mode edge 1 masked interrupt status.
Definition: cc2538_uart.h:161
cc2538_reg_t TXFE
UART transmit FIFO empty.
Definition: cc2538_uart.h:57
cc2538_reg_t RTIM
UART receive time-out interrupt mask.
Definition: cc2538_uart.h:128
cc2538_reg_t PEN
UART parity enable.
Definition: cc2538_uart.h:74
cc2538_reg_t OEMIS
UART overrun error masked interrupt status.
Definition: cc2538_uart.h:157
cc2538_reg_t STP2
UART two stop bits select.
Definition: cc2538_uart.h:76
cc2538_reg_t RSR
UART receive status and error clear.
Definition: cc2538_uart.h:39
CC2538 MCU interrupt and register definitions.
cc2538_reg_t MIS
UART Masked Interrupt Status.
Definition: cc2538_uart.h:148
cc2538_reg_t FBRD
UART Fractional Baud-Rate Divisor.
Definition: cc2538_uart.h:65
cc2538_reg_t RTSEN
U1RTS Hardware flow control enable.
Definition: cc2538_uart.h:101
cc2538_reg_t PEMIS
UART parity error masked interrupt status.
Definition: cc2538_uart.h:155
cc2538_reg_t IM
UART Interrupt Mask.
Definition: cc2538_uart.h:123
cc2538_reg_t LMSBMIS
LIN mode sync break masked interrupt status.
Definition: cc2538_uart.h:160
cc2538_reg_t IBRD
UART Integer Baud-Rate Divisor.
Definition: cc2538_uart.h:64
cc2538_reg_t PP
UART Peripheral Properties.
Definition: cc2538_uart.h:177
cc2538_reg_t LME5MIS
LIN mode edge 5 masked interrupt status.
Definition: cc2538_uart.h:162
cc2538_reg_t RXFF
UART receive FIFO full.
Definition: cc2538_uart.h:56
cc2538_reg_t TXIM
UART transmit interrupt mask.
Definition: cc2538_uart.h:127
cc2538_reg_t LTIM
Definition: cc2538_uart.h:172
cc2538_reg_t LIN
LIN mode enable.
Definition: cc2538_uart.h:96
cc2538_reg_t RESERVED11
Reserved bits.
Definition: cc2538_uart.h:93
cc2538_reg_t NINEBITM
9-bit mode interrupt mask
Definition: cc2538_uart.h:134
cc2538_reg_t TXE
UART transmit enable.
Definition: cc2538_uart.h:98
cc2538_reg_t FEIM
UART framing error interrupt mask.
Definition: cc2538_uart.h:129
cc2538_reg_t DR
UART Data Register.
Definition: cc2538_uart.h:33
cc2538_reg_t RESERVED12
Reserved bits.
Definition: cc2538_uart.h:100
cc2538_reg_t RESERVED10
Reserved bits.
Definition: cc2538_uart.h:163
cc2538_reg_t TXIFLSEL
UART transmit interrupt FIFO level select.
Definition: cc2538_uart.h:113
cc2538_reg_t RESERVED9
Reserved bits.
Definition: cc2538_uart.h:158
cc2538_reg_t BEIM
UART break error interrupt mask.
Definition: cc2538_uart.h:131
cc2538_reg_t HSE
High-speed enable.
Definition: cc2538_uart.h:95
UART component registers.
Definition: cc2538_uart.h:32
cc2538_reg_t BUSY
UART busy.
Definition: cc2538_uart.h:53
cc2538_reg_t ECR
UART receive status and error clear.
Definition: cc2538_uart.h:40
cc2538_reg_t LMSBIM
LIN mode sync break interrupt mask.
Definition: cc2538_uart.h:135
cc2538_reg_t RESERVED
Reserved bits.
Definition: cc2538_uart.h:80
cc2538_reg_t LBE
UART loop back enable.
Definition: cc2538_uart.h:97
cc2538_reg_t TXMIS
UART transmit masked interrupt status.
Definition: cc2538_uart.h:152
cc2538_reg_t NINEBITADDR
UART 9-bit self Address.
Definition: cc2538_uart.h:174
cc2538_reg_t RESERVED13
Reserved bits.
Definition: cc2538_uart.h:103
cc2538_reg_t NINEBITAMASK
UART 9-bit self Address Mask.
Definition: cc2538_uart.h:175
cc2538_reg_t ILPR
UART IrDA Low-Power Register.
Definition: cc2538_uart.h:63
cc2538_reg_t LCRH
UART Line Control Register.
Definition: cc2538_uart.h:71
volatile uint32_t cc2538_reg_t
Least-significant 32 bits of the IEEE address.
Definition: cc2538.h:124
cc2538_reg_t DMACTL
UART DMA Control.
Definition: cc2538_uart.h:168
cc2538_reg_t RXE
UART receive enable.
Definition: cc2538_uart.h:99
cc2538_reg_t RXMIS
UART receive masked interrupt status.
Definition: cc2538_uart.h:151
cc2538_reg_t BRK
UART send break.
Definition: cc2538_uart.h:73