cc2538_ssi.h
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1 /*
2  * Copyright (C) 2014 Loci Controls Inc.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef CC2538_SSI_H
20 #define CC2538_SSI_H
21 
22 #include "cc2538.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
31 typedef struct {
32  union {
34  struct {
41  } CR0bits;
42  };
43 
44  union {
46  struct {
51  cc2538_reg_t RESERVED : 28;
52  } CR1bits;
53  };
54 
57  union {
59  struct {
65  cc2538_reg_t RESERVED : 27;
66  } SRbits;
67  };
75 } cc2538_ssi_t;
76 
77 #define SSI0 ( (cc2538_ssi_t*)0x40008000 )
78 #define SSI1 ( (cc2538_ssi_t*)0x40009000 )
84 #define SSI_CR0_DSS(x) ((x - 1) << 0)
85 #define SSI_CR0_SPO (1 << 6)
86 #define SSI_CR0_SPH (1 << 7)
87 
93 #define SSI_CR1_LBM (1 << 0)
94 #define SSI_CR1_SSE (1 << 1)
95 #define SSI_CR1_MS (1 << 2)
96 #define SSI_CR1_SOD (1 << 3)
97 
103 #define SSI_SR_TFE (1 << 0)
104 #define SSI_SR_TNF (1 << 1)
105 #define SSI_SR_RNE (1 << 2)
106 #define SSI_SR_RFF (1 << 3)
107 #define SSI_SR_BSY (1 << 4)
108 
114 #define SSI_SS_PIOSC (1 << 0)
115 #define SSI_SS_DSEN (1 << 2)
116 #define SSI_SS_SYSDIV (0)
117 #define SSI_SS_IODIV (SSI_SS_PIOSC)
118 
120 #ifdef __cplusplus
121 } /* end extern "C" */
122 #endif
123 
124 #endif /* CC2538_SSI_H */
125 
cc2538_reg_t TFE
SSI transmit FIFO empty.
Definition: cc2538_ssi.h:60
cc2538_reg_t MIS
SSI Masked Interrupt Status register.
Definition: cc2538_ssi.h:71
cc2538_reg_t IM
SSI Interrupt Mask register.
Definition: cc2538_ssi.h:69
cc2538_reg_t RIS
SSI Raw Interrupt Status register.
Definition: cc2538_ssi.h:70
cc2538_reg_t CR0
SSI Control Register 0.
Definition: cc2538_ssi.h:33
cc2538_reg_t CR1
SSI Control Register 1.
Definition: cc2538_ssi.h:45
cc2538_reg_t DR
SSI Data register.
Definition: cc2538_ssi.h:55
cc2538_reg_t CPSR
SSI Clock Register.
Definition: cc2538_ssi.h:68
cc2538_reg_t DMACTL
SSI uDMA Control Register.
Definition: cc2538_ssi.h:73
CC2538 MCU interrupt and register definitions.
cc2538_reg_t SCR
SSI serial clock rate.
Definition: cc2538_ssi.h:39
cc2538_reg_t RESERVED
Reserved bits.
Definition: cc2538_ssi.h:40
cc2538_reg_t SSE
SSI synchronous serial port enable.
Definition: cc2538_ssi.h:48
cc2538_reg_t BSY
SSI busy bit.
Definition: cc2538_ssi.h:64
cc2538_reg_t RFF
SSI receive FIFO full.
Definition: cc2538_ssi.h:63
cc2538_reg_t MS
SSI master and slave select.
Definition: cc2538_ssi.h:49
cc2538_reg_t FRF
SSI frame format select.
Definition: cc2538_ssi.h:36
cc2538_reg_t SPH
SSI serial clock phase.
Definition: cc2538_ssi.h:38
cc2538_reg_t SPO
SSI serial clock polarity.
Definition: cc2538_ssi.h:37
cc2538_reg_t SR
SSI FIFO/busy Status Register.
Definition: cc2538_ssi.h:58
cc2538_reg_t RNE
SSI receive FIFO not empty.
Definition: cc2538_ssi.h:62
cc2538_reg_t CC
SSI clock configuration.
Definition: cc2538_ssi.h:74
cc2538_reg_t TNF
SSI transmit FIFO not full.
Definition: cc2538_ssi.h:61
cc2538_reg_t DSS
SSI data size select.
Definition: cc2538_ssi.h:35
cc2538_reg_t ICR
SSI Interrupt Clear Register.
Definition: cc2538_ssi.h:72
volatile uint32_t cc2538_reg_t
Least-significant 32 bits of the IEEE address.
Definition: cc2538.h:124
cc2538_reg_t SOD
SSI slave mode output disable.
Definition: cc2538_ssi.h:50
cc2538_reg_t LBM
SSI loop-back mode.
Definition: cc2538_ssi.h:47
SSI component registers.
Definition: cc2538_ssi.h:31