cc2538_gpio.h
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1 /*
2  * Copyright (C) 2014 Loci Controls Inc.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
24 #ifndef CC2538_GPIO_H
25 #define CC2538_GPIO_H
26 
27 #include <stdint.h>
28 
29 #include "cc2538.h"
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
39 enum {
40  PORT_A = 0,
41  PORT_B = 1,
42  PORT_C = 2,
43  PORT_D = 3,
44 };
47 #define GPIO_PORT_SHIFT 3
48 #define GPIO_BITS_PER_PORT ( 1 << GPIO_PORT_SHIFT )
49 #define GPIO_BIT_MASK ( GPIO_BITS_PER_PORT - 1 )
58 #define PIN_MASK(n) ( 1 << (n) )
59 
67 #define GPIO_NUM_TO_PORT_NUM(gpio_num) ( (gpio_num) >> GPIO_PORT_SHIFT )
68 
76 #define GPIO_BIT_NUM(gpio_num) ( (gpio_num) & GPIO_BIT_MASK )
77 
86 #define GPIO_PXX_TO_NUM(port_num, bit_num) ( ((port_num) << GPIO_PORT_SHIFT) | (bit_num) )
87 
95 #define GPIO_NUM_TO_DEV(gpio_num) ( GPIO_A + GPIO_NUM_TO_PORT_NUM(gpio_num) )
96 
102 #define gpio_hardware_control(gpio_num) ( GPIO_NUM_TO_DEV(gpio_num)->AFSEL |= PIN_MASK(GPIO_BIT_NUM(gpio_num)) )
103 
109 #define gpio_software_control(gpio_num) ( GPIO_NUM_TO_DEV(gpio_num)->AFSEL &= ~PIN_MASK(GPIO_BIT_NUM(gpio_num)) )
110 
116 #define gpio_dir_output(gpio_num) ( GPIO_NUM_TO_DEV(gpio_num)->DIR |= PIN_MASK(GPIO_BIT_NUM(gpio_num)) )
117 
123 #define gpio_dir_input(gpio_num) ( GPIO_NUM_TO_DEV(gpio_num)->DIR &= ~PIN_MASK(GPIO_BIT_NUM(gpio_num)) )
124 
130 #define cc2538_gpio_read(gpio_num) ( (GPIO_NUM_TO_DEV(gpio_num)->DATA >> GPIO_BIT_NUM(gpio_num)) & 1 )
131 
137 #define cc2538_gpio_clear(gpio_num) ( GPIO_NUM_TO_DEV(gpio_num)->DATA &= ~PIN_MASK(GPIO_BIT_NUM(gpio_num)) )
138 
145 enum {
146  GPIO_PA0 = GPIO_PXX_TO_NUM(PORT_A, 0),
147  GPIO_PA1 = GPIO_PXX_TO_NUM(PORT_A, 1),
148  GPIO_PA2 = GPIO_PXX_TO_NUM(PORT_A, 2),
149  GPIO_PA3 = GPIO_PXX_TO_NUM(PORT_A, 3),
150  GPIO_PA4 = GPIO_PXX_TO_NUM(PORT_A, 4),
151  GPIO_PA5 = GPIO_PXX_TO_NUM(PORT_A, 5),
152  GPIO_PA6 = GPIO_PXX_TO_NUM(PORT_A, 6),
153  GPIO_PA7 = GPIO_PXX_TO_NUM(PORT_A, 7),
154  GPIO_PB0 = GPIO_PXX_TO_NUM(PORT_B, 0),
155  GPIO_PB1 = GPIO_PXX_TO_NUM(PORT_B, 1),
156  GPIO_PB2 = GPIO_PXX_TO_NUM(PORT_B, 2),
157  GPIO_PB3 = GPIO_PXX_TO_NUM(PORT_B, 3),
158  GPIO_PB4 = GPIO_PXX_TO_NUM(PORT_B, 4),
159  GPIO_PB5 = GPIO_PXX_TO_NUM(PORT_B, 5),
160  GPIO_PB6 = GPIO_PXX_TO_NUM(PORT_B, 6),
161  GPIO_PB7 = GPIO_PXX_TO_NUM(PORT_B, 7),
162  GPIO_PC0 = GPIO_PXX_TO_NUM(PORT_C, 0),
163  GPIO_PC1 = GPIO_PXX_TO_NUM(PORT_C, 1),
164  GPIO_PC2 = GPIO_PXX_TO_NUM(PORT_C, 2),
165  GPIO_PC3 = GPIO_PXX_TO_NUM(PORT_C, 3),
166  GPIO_PC4 = GPIO_PXX_TO_NUM(PORT_C, 4),
167  GPIO_PC5 = GPIO_PXX_TO_NUM(PORT_C, 5),
168  GPIO_PC6 = GPIO_PXX_TO_NUM(PORT_C, 6),
169  GPIO_PC7 = GPIO_PXX_TO_NUM(PORT_C, 7),
170  GPIO_PD0 = GPIO_PXX_TO_NUM(PORT_D, 0),
171  GPIO_PD1 = GPIO_PXX_TO_NUM(PORT_D, 1),
172  GPIO_PD2 = GPIO_PXX_TO_NUM(PORT_D, 2),
173  GPIO_PD3 = GPIO_PXX_TO_NUM(PORT_D, 3),
174  GPIO_PD4 = GPIO_PXX_TO_NUM(PORT_D, 4),
175  GPIO_PD5 = GPIO_PXX_TO_NUM(PORT_D, 5),
176  GPIO_PD6 = GPIO_PXX_TO_NUM(PORT_D, 6),
177  GPIO_PD7 = GPIO_PXX_TO_NUM(PORT_D, 7),
178 };
184 typedef struct {
185  cc2538_reg_t RESERVED1[255];
196  cc2538_reg_t RESERVED2[63];
199  cc2538_reg_t RESERVED3[118];
202  cc2538_reg_t RESERVED4[2];
204  cc2538_reg_t RESERVED5[1];
208  cc2538_reg_t RESERVED6[567];
209 } cc2538_gpio_t;
210 
214 #define GPIO_BASE (0x400d9000)
215 
220 #define GPIO_PORTNUM_SHIFT (12U)
221 #define GPIO_PORTNUM_MASK (0x00007000)
222 #define GPIO_PIN_MASK (0x00000007)
223 #define GPIO_PORT_MASK (0xfffff000)
231 #define GPIO_A ((cc2538_gpio_t *)0x400d9000)
232 #define GPIO_B ((cc2538_gpio_t *)0x400da000)
233 #define GPIO_C ((cc2538_gpio_t *)0x400db000)
234 #define GPIO_D ((cc2538_gpio_t *)0x400dc000)
240  typedef struct {
241  cc2538_reg_t SEL[32];
242  cc2538_reg_t OVER[32];
243  cc2538_reg_t PINS[21];
244  } cc2538_ioc_t;
245 
250  typedef enum {
251  UART0_TXD = 0,
279  typedef enum {
280  UART0_RXD = 0,
307  typedef enum {
308  OVERRIDE_DISABLE = 0x0,
309  OVERRIDE_ANALOG = 0x1,
310  OVERRIDE_PULLDOWN = 0x2,
311  OVERRIDE_PULLUP = 0x4,
312  OVERRIDE_ENABLE = 0x8,
314 
321 #define IOC_OVERRIDE_OE 0x00000008
322 #define IOC_OVERRIDE_PUE 0x00000004
323 #define IOC_OVERRIDE_PDE 0x00000002
324 #define IOC_OVERRIDE_ANA 0x00000001
325 #define IOC_OVERRIDE_DIS 0x00000000
331 #define IOC ((cc2538_ioc_t *)0x400d4000)
332 
339 #define IOC_PXX_OVER (IOC->OVER)
340 #define IOC_PXX_SEL (IOC->SEL)
341 
343 #ifdef __cplusplus
344 } /* end extern "C" */
345 #endif
346 
347 #endif /* CC2538_GPIO_H */
348 
PC3.
Definition: cc2538_gpio.h:165
PD4.
Definition: cc2538_gpio.h:174
SSI0 STXSER EN.
Definition: cc2538_gpio.h:257
PB6.
Definition: cc2538_gpio.h:160
PB1.
Definition: cc2538_gpio.h:155
SSI1 RXD.
Definition: cc2538_gpio.h:288
PB3.
Definition: cc2538_gpio.h:157
SSI1 STXSER EN.
Definition: cc2538_gpio.h:261
GPT1 OCP1.
Definition: cc2538_gpio.h:295
cc2538_reg_t IRQ_DETECT_ACK
GPIO_A IRQ Detect ACK register.
Definition: cc2538_gpio.h:205
SSI0 TXD.
Definition: cc2538_gpio.h:254
cc2538_ioc_over_t
Values to override pin configuration.
Definition: cc2538_gpio.h:307
PD0.
Definition: cc2538_gpio.h:170
cc2538_reg_t IC
GPIO_A Interrupt Clear register.
Definition: cc2538_gpio.h:194
SSI1 CLK IN.
Definition: cc2538_gpio.h:290
I2C SDA IN.
Definition: cc2538_gpio.h:291
PC4.
Definition: cc2538_gpio.h:166
PC1.
Definition: cc2538_gpio.h:163
PA0.
Definition: cc2538_gpio.h:146
GPT3 OCP1.
Definition: cc2538_gpio.h:299
cc2538_ioc_pin_t
Definition: cc2538_gpio.h:279
cc2538_reg_t GPIOLOCK
GPIO_A Lock register.
Definition: cc2538_gpio.h:197
SSI0 RXD.
Definition: cc2538_gpio.h:284
UART1 RXD.
Definition: cc2538_gpio.h:282
SSI1 FSS IN.
Definition: cc2538_gpio.h:289
GPT3 ICP2.
Definition: cc2538_gpio.h:271
SSI0 CLKOUT.
Definition: cc2538_gpio.h:255
PD1.
Definition: cc2538_gpio.h:171
GPT3 OCP2.
Definition: cc2538_gpio.h:300
#define GPIO_PXX_TO_NUM(port_num, bit_num)
Generate a GPIO number given a port and bit number.
Definition: cc2538_gpio.h:86
cc2538_reg_t P_EDGE_CTRL
GPIO_A The Port Edge Control register.
Definition: cc2538_gpio.h:201
PC6.
Definition: cc2538_gpio.h:168
GPT0 OCP1.
Definition: cc2538_gpio.h:293
PA5.
Definition: cc2538_gpio.h:151
GPT2 OCP1.
Definition: cc2538_gpio.h:297
PB4.
Definition: cc2538_gpio.h:158
SSI1 FSSOUT.
Definition: cc2538_gpio.h:260
GPT2 OCP2.
Definition: cc2538_gpio.h:298
PC2.
Definition: cc2538_gpio.h:164
cc2538_reg_t RIS
GPIO_A Raw Interrupt Status register.
Definition: cc2538_gpio.h:192
SSI1 CLK.
Definition: cc2538_gpio.h:287
PA7.
Definition: cc2538_gpio.h:153
cc2538_reg_t PMUX
GPIO_A The PMUX register.
Definition: cc2538_gpio.h:200
CC2538 MCU interrupt and register definitions.
cc2538_reg_t PI_IEN
GPIO_A The Power-up Interrupt Enable register.
Definition: cc2538_gpio.h:203
PC7.
Definition: cc2538_gpio.h:169
cc2538_reg_t MIS
GPIO_A Masked Interrupt Status register.
Definition: cc2538_gpio.h:193
GPT1 ICP2.
Definition: cc2538_gpio.h:267
PB5.
Definition: cc2538_gpio.h:159
UART0 TXD.
Definition: cc2538_gpio.h:251
GPT1 ICP1.
Definition: cc2538_gpio.h:266
cc2538_reg_t DIR
GPIO_A data direction register.
Definition: cc2538_gpio.h:187
cc2538_reg_t IBE
GPIO_A Interrupt Both-Edges register.
Definition: cc2538_gpio.h:189
PD2.
Definition: cc2538_gpio.h:172
PB0.
Definition: cc2538_gpio.h:154
cc2538_reg_t DATA
GPIO_A Data Register.
Definition: cc2538_gpio.h:186
PD6.
Definition: cc2538_gpio.h:176
GPT2 ICP2.
Definition: cc2538_gpio.h:269
SSI0 FSSOUT.
Definition: cc2538_gpio.h:256
UART1 TXD.
Definition: cc2538_gpio.h:253
GPT0 OCP2.
Definition: cc2538_gpio.h:294
PD5.
Definition: cc2538_gpio.h:175
cc2538_reg_t AFSEL
GPIO_A Alternate Function / mode control select register.
Definition: cc2538_gpio.h:195
I2C CMSSCL.
Definition: cc2538_gpio.h:263
PA1.
Definition: cc2538_gpio.h:147
PA4.
Definition: cc2538_gpio.h:150
I2C SCL IN.
Definition: cc2538_gpio.h:292
cc2538_reg_t IRQ_DETECT_UNMASK
GPIO_A IRQ Detect ACK for masked interrupts.
Definition: cc2538_gpio.h:207
PB2.
Definition: cc2538_gpio.h:156
cc2538_reg_t IEV
GPIO_A Interrupt Event Register.
Definition: cc2538_gpio.h:190
SSI0 CLK.
Definition: cc2538_gpio.h:283
UART1 RTS.
Definition: cc2538_gpio.h:252
cc2538_reg_t GPIOCR
GPIO_A Commit Register.
Definition: cc2538_gpio.h:198
GPT0 ICP2.
Definition: cc2538_gpio.h:265
GPT3 ICP1.
Definition: cc2538_gpio.h:270
SSI1 CLKOUT.
Definition: cc2538_gpio.h:259
GPT0 ICP1.
Definition: cc2538_gpio.h:264
UART1 CTS.
Definition: cc2538_gpio.h:281
PA2.
Definition: cc2538_gpio.h:148
SSI0 FSS IN.
Definition: cc2538_gpio.h:285
GPT2 ICP1.
Definition: cc2538_gpio.h:268
PD7.
Definition: cc2538_gpio.h:177
SSI1 TXD.
Definition: cc2538_gpio.h:258
I2C CMSSDA.
Definition: cc2538_gpio.h:262
SSI0 CLK IN.
Definition: cc2538_gpio.h:286
PA6.
Definition: cc2538_gpio.h:152
cc2538_reg_t IE
GPIO_A Interrupt mask register.
Definition: cc2538_gpio.h:191
cc2538_reg_t IS
GPIO_A Interrupt Sense register.
Definition: cc2538_gpio.h:188
IOC port component registers.
Definition: cc2538_gpio.h:240
volatile uint32_t cc2538_reg_t
Least-significant 32 bits of the IEEE address.
Definition: cc2538.h:124
cc2538_ioc_sel_t
Definition: cc2538_gpio.h:250
cc2538_reg_t USB_IRQ_ACK
GPIO_A IRQ Detect ACK for USB.
Definition: cc2538_gpio.h:206
PC0.
Definition: cc2538_gpio.h:162
GPT1 OCP2.
Definition: cc2538_gpio.h:296
GPIO port component registers.
Definition: cc2538_gpio.h:184
PA3.
Definition: cc2538_gpio.h:149
PC5.
Definition: cc2538_gpio.h:167
PB7.
Definition: cc2538_gpio.h:161
UART0 RXD.
Definition: cc2538_gpio.h:280
PD3.
Definition: cc2538_gpio.h:173