cc2538/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  * 2017 HAW Hamburg
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include <stdint.h>
25 #include <stdio.h>
26 
27 #include "cpu.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
36 #define CPUID_ADDR (&IEEE_ADDR_MSWORD)
37 
40 #define CPUID_LEN (8U)
41 
46 #define HAVE_GPIO_T
47 typedef uint32_t gpio_t;
54 #define PROVIDES_PM_SET_LOWEST_CORTEXM
55 
61 #define PORTNUM_MASK (0x00007000)
62 #define PORTNUM_SHIFT (12U)
63 #define PIN_MASK (0x00000007)
64 #define GPIO_MASK (0xfffff000)
73 #define GPIO_PIN(port, pin) (gpio_t)(((uint32_t)GPIO_A + \
74  (port << PORTNUM_SHIFT)) | pin)
75 
83 static inline cc2538_gpio_t *gpio(gpio_t pin)
84 {
85  return (cc2538_gpio_t *)(pin & GPIO_MASK);
86 }
87 
95 static inline uint8_t gpio_port_num(gpio_t pin)
96 {
97  return (uint8_t)((pin & PORTNUM_MASK) >> PORTNUM_SHIFT) - 1;
98 }
99 
107 static inline uint8_t gpio_pin_num(gpio_t pin)
108 {
109  return (uint8_t)(pin & PIN_MASK);
110 }
111 
119 static inline uint32_t gpio_pin_mask(gpio_t pin)
120 {
121  return (1 << (pin & PIN_MASK));
122 }
123 
131 static inline uint8_t gpio_pp_num(gpio_t pin)
132 {
133  return (uint8_t)((gpio_port_num(pin) * 8) + gpio_pin_num(pin));
134 }
135 
143 void gpio_init_af(gpio_t pin, int sel, int over);
144 
148 #define GPIO_UNDEF 99
149 
153 typedef struct {
154  gpio_t scl_pin;
155  gpio_t sda_pin;
156 } i2c_conf_t;
157 
162 #define PERIPH_SPI_NEEDS_INIT_CS
163 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
164 #define PERIPH_SPI_NEEDS_TRANSFER_REG
165 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
166 
172 #define HAVE_GPIO_MODE_T
173 typedef enum {
174  GPIO_IN = ((uint8_t)0x00),
177  GPIO_OUT = ((uint8_t)IOC_OVERRIDE_OE),
178  GPIO_OD = (0xff),
179  GPIO_OD_PU = (0xff)
180 } gpio_mode_t;
187 #define HAVE_SPI_MODE_T
188 typedef enum {
190  SPI_MODE_1 = (SSI_CR0_SPH),
191  SPI_MODE_2 = (SSI_CR0_SPO),
192  SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH)
193 } spi_mode_t;
200 #define HAVE_SPI_CLK_T
201 typedef enum {
207 } spi_clk_t;
213 typedef struct {
214  uint8_t cpsr;
215  uint8_t scr;
217 
222 typedef struct {
224  gpio_t mosi_pin;
225  gpio_t miso_pin;
226  gpio_t sck_pin;
227  gpio_t cs_pin;
228 } spi_conf_t;
237 typedef struct {
238  uint_fast8_t chn;
239  uint_fast8_t cfg;
240 } timer_conf_t;
241 
246 #define HAVE_ADC_RES_T
247 typedef enum {
248  ADC_RES_6BIT = (0xa00),
249  ADC_RES_7BIT = (0 << 4),
250  ADC_RES_8BIT = (0xb00),
251  ADC_RES_9BIT = (1 << 4),
252  ADC_RES_10BIT = (2 << 4),
253  ADC_RES_12BIT = (3 << 4),
254  ADC_RES_14BIT = (0xc00),
255  ADC_RES_16BIT = (0xd00),
256 } adc_res_t;
262 typedef gpio_t adc_conf_t;
263 
268 #define SOC_ADC_ADCCON3_EREF (0x000000C0)
269 #define SOC_ADC_ADCCON3_EDIV (0x00000030)
270 #define SOC_ADC_ADCCON3_ECH (0x0000000F)
277 #define SOC_ADC_ADCCON_REF_INT (0 << 6)
278 #define SOC_ADC_ADCCON_REF_EXT (1 << 6)
279 #define SOC_ADC_ADCCON_REF_AVDD5 (2 << 6)
280 #define SOC_ADC_ADCCON_REF_DIFF (3 << 6)
281 #define SOC_ADC_ADCCON_CH_GND (0xC)
287 #define SOC_ADC_ADCCON1_EOC_MASK (0x80)
288 
293 #define SOC_ADC_ADCL_MASK (0x000000FC)
294 #define SOC_ADC_ADCH_MASK (0x000000FF)
295 
301 #define SOCADC_7_BIT_RSHIFT (9U)
302 #define SOCADC_9_BIT_RSHIFT (7U)
303 #define SOCADC_10_BIT_RSHIFT (6U)
304 #define SOCADC_12_BIT_RSHIFT (4U)
307 #ifdef __cplusplus
308 }
309 #endif
310 
311 #include "periph/dev_enums.h"
312 
313 #endif /* PERIPH_CPU_H */
314 
CPOL=0, CPHA=1.
ADC resolution: 7 bit.
I2C configuration options.
gpio_t cs_pin
pin used for CS
ADC resolution: 12 bit.
void gpio_init_af(gpio_t pin, int sel, int over)
Configure an alternate function for the given pin.
ADC resolution: 9 bit.
#define PORTNUM_SHIFT
bit shift for GPIO port
#define PORTNUM_MASK
bit mask for GPIO port [0-3]
gpio_t miso_pin
pin used for MISO
gpio_t scl_pin
pin used for SCL
CPOL=0, CPHA=0.
drive the SPI bus with 100KHz
drive the SPI bus with 400KHz
static uint8_t gpio_port_num(gpio_t pin)
Helper function to get port number for gpio pin.
#define PIN_MASK
bit mask for GPIO pin [0-7]
#define IOC_OVERRIDE_PUE
Pull Up Enable.
Definition: cc2538_gpio.h:262
static uint32_t gpio_pin_mask(gpio_t pin)
Helper function to get bit mask for gpio pin number.
static cc2538_gpio_t * gpio(gpio_t pin)
Access GPIO low-level device.
uint_fast8_t cfg
timer config word
not supported by hardware
Device enumerations for backward compatibility with existing peripheral driver implementations.
#define IOC_OVERRIDE_PDE
Pull Down Enable.
Definition: cc2538_gpio.h:263
ADC resolution: 10 bit.
CPOL=1, CPHA=1.
#define GPIO_MASK
bit mask for GPIO port addr
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
gpio_t adc_conf_t
ADC configuration wrapper.
not supported by hardware
Datafields for static SPI clock configuration values.
gpio_t sck_pin
pin used for SCK
drive the SPI bus with 5MHz
not supported by hardware
uint_fast8_t chn
number of channels
not supported by hardware
drive the SPI bus with 10MHz
drive the SPI bus with 1MHz
static uint8_t gpio_pin_num(gpio_t pin)
Helper function to get pin number for gpio pin.
#define IOC_OVERRIDE_OE
Output Enable.
Definition: cc2538_gpio.h:261
stdio.h wrapper for MSP430
input, no pull
uint8_t scr
SCR clock divider.
not supported
gpio_t sda_pin
pin used for SDA
CPOL=1, CPHA=0.
SPI module configuration options.
input, pull-down
uint8_t cpsr
CPSR clock divider.
Timer configuration.
GPIO port component registers.
Definition: cc2538_gpio.h:195
gpio_t mosi_pin
pin used for MOSI
SSI component registers.
Definition: cc2538_ssi.h:31
static uint8_t gpio_pp_num(gpio_t pin)
Helper function to get CC2538 gpio number from port and pin.
cc2538_ssi_t * dev
SSI device.