The friendly Operating System for the Internet of Things
cc2538/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CPU_H
20 #define PERIPH_CPU_H
21 
22 #include <stdint.h>
23 
24 #include "cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
33 #define CPUID_LEN (8U)
34 
39 #define HAVE_GPIO_T
40 typedef uint32_t gpio_t;
49 #define GPIO_PIN(port, pin) (gpio_t)(((uint32_t)GPIO_A + (port << 12)) | pin)
50 
54 #define GPIO_UNDEF 99
55 
59 typedef struct {
60  gpio_t scl_pin;
61  gpio_t sda_pin;
62 } i2c_conf_t;
63 
68 #define PERIPH_SPI_NEEDS_INIT_CS
69 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
70 #define PERIPH_SPI_NEEDS_TRANSFER_REG
71 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
72 
78 #define HAVE_GPIO_MODE_T
79 typedef enum {
80  GPIO_IN = ((uint8_t)0x00),
83  GPIO_OUT = ((uint8_t)IOC_OVERRIDE_OE),
84  GPIO_OD = (0xff),
85  GPIO_OD_PU = (0xff)
86 } gpio_mode_t;
93 #define HAVE_SPI_MODE_T
94 typedef enum {
95  SPI_MODE_0 = 0,
96  SPI_MODE_1 = (SSI_CR0_SPH),
97  SPI_MODE_2 = (SSI_CR0_SPO),
98  SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH)
99 } spi_mode_t;
106 #define HAVE_SPI_CLK_T
107 typedef enum {
113 } spi_clk_t;
119 typedef struct {
120  uint8_t cpsr;
121  uint8_t scr;
123 
128 typedef struct {
130  gpio_t mosi_pin;
131  gpio_t miso_pin;
132  gpio_t sck_pin;
133  gpio_t cs_pin;
134 } spi_conf_t;
140 typedef struct {
142  uint_fast8_t channels;
143  uint_fast8_t cfg;
144 } timer_conf_t;
145 
146 #ifdef __cplusplus
147 }
148 #endif
149 
150 #include "periph/dev_enums.h"
151 
152 #endif /* PERIPH_CPU_H */
153 
uint_fast8_t channels
number of channels
CPOL=0, CPHA=1.
GPTIMER component registers.
I2C configuration options.
gpio_t cs_pin
pin used for CS
gpio_t miso_pin
pin used for MISO
gpio_t scl_pin
pin used for SCL
CPOL=0, CPHA=0.
drive the SPI bus with 100KHz
drive the SPI bus with 400KHz
#define IOC_OVERRIDE_PUE
Pull Up Enable.
Definition: cc2538_gpio.h:262
uint_fast8_t cfg
timer config word
Device enumerations for backward compatibility with existing peripheral driver implementations.
#define IOC_OVERRIDE_PDE
Pull Down Enable.
Definition: cc2538_gpio.h:263
CPOL=1, CPHA=1.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
Datafields for static SPI clock configuration values.
gpio_t sck_pin
pin used for SCK
drive the SPI bus with 5MHz
drive the SPI bus with 10MHz
drive the SPI bus with 1MHz
input, pull-up
#define IOC_OVERRIDE_OE
Output Enable.
Definition: cc2538_gpio.h:261
input, no pull
uint8_t scr
SCR clock divider.
not supported
gpio_t sda_pin
pin used for SDA
CPOL=1, CPHA=0.
SPI configuration data structure.
input, pull-down
cc2538_gptimer_t * dev
timer device
uint8_t cpsr
CPSR clock divider.
Timer configuration data.
gpio_t mosi_pin
pin used for MOSI
SSI component registers.
Definition: cc2538_ssi.h:31
cc2538_ssi_t * dev
SSI device.