periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  * 2017 HAW Hamburg
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include <stdint.h>
25 #include <stdio.h>
26 
27 #include "vendor/hw_soc_adc.h"
28 
29 #include "cpu.h"
30 #include "vendor/hw_ssi.h"
31 #include "vendor/hw_uart.h"
32 
33 #ifdef __cplusplus
34 extern "C" {
35 #endif
36 
40 #define CPUID_ADDR (&IEEE_ADDR_MSWORD)
41 
45 #define CPUID_LEN (8U)
46 
51 #define HAVE_GPIO_T
52 typedef uint32_t gpio_t;
59 #define PROVIDES_PM_SET_LOWEST_CORTEXM
60 
65 #define GPIO_UNDEF (0xffffffff)
66 
70 #define GPIO_MUX_NONE (0xff)
71 
77 #define GPIO_PIN(port, pin) (gpio_t)(((uint32_t)GPIO_BASE + \
78  (port << GPIO_PORTNUM_SHIFT)) | pin)
79 
87 void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over);
88 
97 void gpio_init_mux(gpio_t pin, uint8_t over, uint8_t sel, uint8_t func);
98 
103 #define PERIPH_I2C_NEED_READ_REG
104 #define PERIPH_I2C_NEED_READ_REGS
105 #define PERIPH_I2C_NEED_WRITE_REG
106 #define PERIPH_I2C_NEED_WRITE_REGS
107 
113 #define HAVE_I2C_SPEED_T
114 typedef enum {
115  I2C_SPEED_LOW = 0x01,
116  I2C_SPEED_NORMAL = 100000U,
117  I2C_SPEED_FAST = 400000U,
119  I2C_SPEED_HIGH = 0x03,
120 } i2c_speed_t;
125 typedef struct {
127  gpio_t scl_pin;
128  gpio_t sda_pin;
129 } i2c_conf_t;
130 
135 #define PERIPH_SPI_NEEDS_INIT_CS
136 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
137 #define PERIPH_SPI_NEEDS_TRANSFER_REG
138 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
139 
145 #define HAVE_GPIO_MODE_T
146 typedef enum {
147  GPIO_IN = ((uint8_t)OVERRIDE_DISABLE),
148  GPIO_IN_ANALOG = ((uint8_t)OVERRIDE_ANALOG),
149  GPIO_IN_PD = ((uint8_t)OVERRIDE_PULLDOWN),
150  GPIO_IN_PU = ((uint8_t)OVERRIDE_PULLUP),
151  GPIO_OUT = ((uint8_t)OVERRIDE_ENABLE),
152  GPIO_OD = (0xff),
153  GPIO_OD_PU = (0xff)
154 } gpio_mode_t;
162 typedef struct {
164  gpio_t rx_pin;
165  gpio_t tx_pin;
166  gpio_t cts_pin;
167  gpio_t rts_pin;
168 } uart_conf_t;
171 #ifndef DOXYGEN
172 
176 #define HAVE_UART_PARITY_T
177 typedef enum {
178  UART_PARITY_NONE = 0,
179  UART_PARITY_EVEN = (UART_LCRH_PEN | UART_LCRH_EPS),
180  UART_PARITY_ODD = UART_LCRH_PEN,
181  UART_PARITY_MARK = (UART_LCRH_PEN | UART_LCRH_SPS),
182  UART_PARITY_SPACE = (UART_LCRH_PEN | UART_LCRH_EPS | UART_LCRH_SPS)
183 } uart_parity_t;
190 #define HAVE_UART_DATA_BITS_T
191 typedef enum {
192  UART_DATA_BITS_5 = (0 << UART_LCRH_WLEN_S),
193  UART_DATA_BITS_6 = (1 << UART_LCRH_WLEN_S),
194  UART_DATA_BITS_7 = (2 << UART_LCRH_WLEN_S),
195  UART_DATA_BITS_8 = (3 << UART_LCRH_WLEN_S),
203 #define HAVE_UART_STOP_BITS_T
204 typedef enum {
205  UART_STOP_BITS_1 = 0,
206  UART_STOP_BITS_2 = UART_LCRH_STP2,
209 #endif /* DOXYGEN */
210 
215 #define HAVE_SPI_MODE_T
216 typedef enum {
218  SPI_MODE_1 = (SSI_CR0_SPH),
219  SPI_MODE_2 = (SSI_CR0_SPO),
220  SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH)
221 } spi_mode_t;
228 #define HAVE_SPI_CLK_T
229 typedef enum {
235 } spi_clk_t;
241 typedef struct {
242  uint8_t cpsr;
243  uint8_t scr;
245 
246 #ifndef BOARD_HAS_SPI_CLK_CONF
247 
254 static const spi_clk_conf_t spi_clk_config[] = {
255  { .cpsr = 64, .scr = 4 }, /* 100khz */
256  { .cpsr = 16, .scr = 4 }, /* 400khz */
257  { .cpsr = 32, .scr = 0 }, /* 1.0MHz */
258  { .cpsr = 2, .scr = 2 }, /* 5.3MHz */
259  { .cpsr = 2, .scr = 1 } /* 8.0MHz */
260 };
261 #endif /* BOARD_HAS_SPI_CLK_CONF */
262 
267 typedef struct {
268  uint8_t num;
269  gpio_t mosi_pin;
270  gpio_t miso_pin;
271  gpio_t sck_pin;
272  gpio_t cs_pin;
273 } spi_conf_t;
282 typedef struct {
283  uint_fast8_t chn;
284  uint_fast8_t cfg;
285 } timer_conf_t;
286 
291 #define HAVE_ADC_RES_T
292 typedef enum {
293  ADC_RES_6BIT = (0xa00),
294  ADC_RES_7BIT = (0 << 4),
295  ADC_RES_8BIT = (0xb00),
296  ADC_RES_9BIT = (1 << 4),
297  ADC_RES_10BIT = (2 << 4),
298  ADC_RES_12BIT = (3 << 4),
299  ADC_RES_14BIT = (0xc00),
300  ADC_RES_16BIT = (0xd00),
301 } adc_res_t;
307 typedef gpio_t adc_conf_t;
308 
313 #define SOC_ADC_ADCCON3_EREF_INT (0 << SOC_ADC_ADCCON3_EREF_S)
314 #define SOC_ADC_ADCCON3_EREF_EXT (1 << SOC_ADC_ADCCON3_EREF_S)
315 #define SOC_ADC_ADCCON3_EREF_AVDD5 (2 << SOC_ADC_ADCCON3_EREF_S)
316 #define SOC_ADC_ADCCON3_EREF_DIFF (3 << SOC_ADC_ADCCON3_EREF_S)
323 #define SOCADC_7_BIT_RSHIFT (9U)
324 #define SOCADC_9_BIT_RSHIFT (7U)
325 #define SOCADC_10_BIT_RSHIFT (6U)
326 #define SOCADC_12_BIT_RSHIFT (4U)
329 #ifdef __cplusplus
330 }
331 #endif
332 
333 #endif /* PERIPH_CPU_H */
334 
fast mode: ~400kbit/s
Definition: periph_cpu.h:117
CPOL=0, CPHA=1.
Definition: periph_cpu.h:218
ADC resolution: 7 bit.
Definition: periph_cpu.h:294
output
Definition: periph_cpu.h:151
not supported
Definition: periph_cpu.h:119
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:163
I2C configuration options.
Definition: periph_cpu.h:125
gpio_t cs_pin
pin used for CS
Definition: periph_cpu.h:272
ADC resolution: 12 bit.
Definition: periph_cpu.h:298
odd parity
Definition: uart.h:131
ADC resolution: 9 bit.
Definition: periph_cpu.h:296
spi_mode_t
adc_res_t
Definition: periph_cpu.h:292
static const spi_clk_conf_t spi_clk_config[]
Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
Definition: periph_cpu.h:254
mark parity
Definition: uart.h:132
uint8_t num
number of SSI device, i.e.
Definition: periph_cpu.h:268
gpio_t miso_pin
pin used for MISO
Definition: periph_cpu.h:270
uart_stop_bits_t
Definition of possible stop bits lengths in a UART frame.
Definition: uart.h:153
gpio_t scl_pin
pin used for SCL
Definition: periph_cpu.h:127
CPOL=0, CPHA=0.
Definition: periph_cpu.h:217
drive the SPI bus with 100KHz
Definition: periph_cpu.h:230
space parity
Definition: uart.h:133
drive the SPI bus with 400KHz
Definition: periph_cpu.h:231
gpio_t rx_pin
pin used for RX
Definition: periph_cpu.h:164
no parity
Definition: uart.h:129
uart_data_bits_t
input, analog
Definition: periph_cpu.h:148
i2c_speed_t
Definition: periph_cpu.h:114
gpio_mode_t
Definition: periph_cpu.h:146
uint_fast8_t cfg
timer config word
Definition: periph_cpu.h:284
gpio_t rts_pin
RTS pin - set to GPIO_UNDEF when not using.
Definition: periph_cpu.h:167
not supported by hardware
Definition: periph_cpu.h:299
uart_parity_t
Definition of possible parity modes.
Definition: uart.h:128
1 stop bit
Definition: uart.h:154
even parity
Definition: uart.h:130
ADC resolution: 10 bit.
Definition: periph_cpu.h:297
CPOL=1, CPHA=1.
Definition: periph_cpu.h:220
2 stop bits
Definition: uart.h:155
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:86
gpio_t adc_conf_t
ADC configuration wrapper.
Definition: periph_cpu.h:307
not supported by hardware
Definition: periph_cpu.h:300
Datafields for static SPI clock configuration values.
Definition: periph_cpu.h:241
gpio_t sck_pin
pin used for SCK
Definition: periph_cpu.h:271
drive the SPI bus with 5MHz
Definition: periph_cpu.h:233
not supported by hardware
Definition: periph_cpu.h:295
uint_fast8_t chn
number of channels
Definition: periph_cpu.h:283
gpio_t tx_pin
pin used for TX
Definition: periph_cpu.h:165
not supported by hardware
Definition: periph_cpu.h:293
drive the SPI bus with 10MHz
Definition: periph_cpu.h:234
i2c_speed_t speed
baudrate used for the bus
Definition: periph_cpu.h:126
drive the SPI bus with 1MHz
Definition: periph_cpu.h:232
input, pull-up
Definition: periph_cpu.h:150
void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over)
Configure an alternate function for the given pin.
void gpio_init_mux(gpio_t pin, uint8_t over, uint8_t sel, uint8_t func)
Configure an alternate function for the given pin.
UART device configuration.
Definition: periph_cpu.h:162
input, no pull
Definition: periph_cpu.h:147
uint8_t scr
SCR clock divider.
Definition: periph_cpu.h:243
gpio_t cts_pin
CTS pin - set to GPIO_UNDEF when not using.
Definition: periph_cpu.h:166
UART component registers.
Definition: cc2538_uart.h:32
not supported
Definition: periph_cpu.h:115
not supported
Definition: periph_cpu.h:152
gpio_t sda_pin
pin used for SDA
Definition: periph_cpu.h:128
CPOL=1, CPHA=0.
Definition: periph_cpu.h:219
SPI configuration structure type.
Definition: periph_cpu.h:267
spi_clk_t
Definition: periph_cpu.h:229
normal mode: ~100kbit/s
Definition: periph_cpu.h:116
input, pull-down
Definition: periph_cpu.h:149
not supported
Definition: periph_cpu.h:153
uint8_t cpsr
CPSR clock divider.
Definition: periph_cpu.h:242
Timer configuration.
Definition: periph_cpu.h:282
gpio_t mosi_pin
pin used for MOSI
Definition: periph_cpu.h:269
not supported
Definition: periph_cpu.h:118