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periph_cpu.h
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1/*
2 * Copyright (C) 2015-2016 Freie Universität Berlin
3 * 2017 HAW Hamburg
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef PERIPH_CPU_H
22#define PERIPH_CPU_H
23
24#include <stdint.h>
25#include <stdio.h>
26
27#include "vendor/hw_soc_adc.h"
28
29#include "cpu.h"
30#include "vendor/hw_ssi.h"
31#include "vendor/hw_uart.h"
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
40#define CPUID_ADDR (&IEEE_ADDR_MSWORD)
41
45#define CPUID_LEN (8U)
46
51#define HAVE_GPIO_T
52typedef uint32_t gpio_t;
59#define PM_NUM_MODES (5)
65#define GPIO_UNDEF (0xffffffff)
66
70#define GPIO_MUX_NONE (0xff)
77#define GPIO_PIN(port, pin) (gpio_t)(((uint32_t)GPIO_BASE + \
78 (port << GPIO_PORTNUM_SHIFT)) | pin)
79
87void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over);
88
97void gpio_init_mux(gpio_t pin, uint8_t over, uint8_t sel, uint8_t func);
98
103#define PERIPH_I2C_NEED_READ_REG
104#define PERIPH_I2C_NEED_READ_REGS
105#define PERIPH_I2C_NEED_WRITE_REG
106#define PERIPH_I2C_NEED_WRITE_REGS
109#ifndef DOXYGEN
114#define HAVE_I2C_SPEED_T
115typedef enum {
116 I2C_SPEED_LOW = 0x01,
117 I2C_SPEED_NORMAL = 100000U,
118 I2C_SPEED_FAST = 400000U,
119 I2C_SPEED_FAST_PLUS = 0x02,
120 I2C_SPEED_HIGH = 0x03,
123#endif /* ndef DOXYGEN */
124
128typedef struct {
129 i2c_speed_t speed;
130 gpio_t scl_pin;
131 gpio_t sda_pin;
132} i2c_conf_t;
133
138#define PERIPH_SPI_NEEDS_INIT_CS
139#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
140#define PERIPH_SPI_NEEDS_TRANSFER_REG
141#define PERIPH_SPI_NEEDS_TRANSFER_REGS
144#ifndef DOXYGEN
149#define HAVE_GPIO_MODE_T
150typedef enum {
151 GPIO_IN = ((uint8_t)OVERRIDE_DISABLE),
152 GPIO_IN_ANALOG = ((uint8_t)OVERRIDE_ANALOG),
153 GPIO_IN_PD = ((uint8_t)OVERRIDE_PULLDOWN),
154 GPIO_IN_PU = ((uint8_t)OVERRIDE_PULLUP),
155 GPIO_OUT = ((uint8_t)OVERRIDE_ENABLE),
156 GPIO_OD = (0xff),
157 GPIO_OD_PU = (0xff)
160#endif /* ndef DOXYGEN */
161
166typedef struct {
168 gpio_t rx_pin;
169 gpio_t tx_pin;
170#ifdef MODULE_PERIPH_UART_HW_FC
171 gpio_t cts_pin;
172 gpio_t rts_pin;
173#endif
177#ifndef DOXYGEN
182#define HAVE_UART_PARITY_T
183typedef enum {
184 UART_PARITY_NONE = 0,
185 UART_PARITY_EVEN = (UART_LCRH_PEN | UART_LCRH_EPS),
186 UART_PARITY_ODD = UART_LCRH_PEN,
187 UART_PARITY_MARK = (UART_LCRH_PEN | UART_LCRH_SPS),
188 UART_PARITY_SPACE = (UART_LCRH_PEN | UART_LCRH_EPS | UART_LCRH_SPS)
196#define HAVE_UART_DATA_BITS_T
197typedef enum {
198 UART_DATA_BITS_5 = (0 << UART_LCRH_WLEN_S),
199 UART_DATA_BITS_6 = (1 << UART_LCRH_WLEN_S),
200 UART_DATA_BITS_7 = (2 << UART_LCRH_WLEN_S),
201 UART_DATA_BITS_8 = (3 << UART_LCRH_WLEN_S),
209#define HAVE_UART_STOP_BITS_T
210typedef enum {
211 UART_STOP_BITS_1 = 0,
212 UART_STOP_BITS_2 = UART_LCRH_STP2,
219#ifndef UART_TXBUF_SIZE
220#define UART_TXBUF_SIZE (64)
221#endif
222
226#define SPI_CS_UNDEF (GPIO_UNDEF)
227
228#ifndef DOXYGEN
233#define HAVE_SPI_CS_T
234typedef uint32_t spi_cs_t;
236#endif
237
242#define HAVE_SPI_MODE_T
243typedef enum {
244 SPI_MODE_0 = 0,
245 SPI_MODE_1 = (SSI_CR0_SPH),
246 SPI_MODE_2 = (SSI_CR0_SPO),
247 SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH)
248} spi_mode_t;
255#define HAVE_SPI_CLK_T
256typedef enum {
257 SPI_CLK_100KHZ = 0,
258 SPI_CLK_400KHZ = 1,
259 SPI_CLK_1MHZ = 2,
260 SPI_CLK_5MHZ = 3,
261 SPI_CLK_10MHZ = 4
262} spi_clk_t;
264#endif /* ndef DOXYGEN */
265
269typedef struct {
270 uint8_t cpsr;
271 uint8_t scr;
273
274#ifndef BOARD_HAS_SPI_CLK_CONF
283 { .cpsr = 64, .scr = 4 }, /* 100khz */
284 { .cpsr = 16, .scr = 4 }, /* 400khz */
285 { .cpsr = 32, .scr = 0 }, /* 1.0MHz */
286 { .cpsr = 2, .scr = 2 }, /* 5.3MHz */
287 { .cpsr = 2, .scr = 1 } /* 8.0MHz */
288};
289#endif /* BOARD_HAS_SPI_CLK_CONF */
290
295typedef struct {
296 uint8_t num;
297 gpio_t mosi_pin;
298 gpio_t miso_pin;
299 gpio_t sck_pin;
301} spi_conf_t;
310typedef struct {
311 uint_fast8_t chn;
312 uint_fast8_t cfg;
314
315#ifndef DOXYGEN
320#define HAVE_ADC_RES_T
321typedef enum {
322 ADC_RES_6BIT = (0xa00),
323 ADC_RES_7BIT = (0 << 4),
324 ADC_RES_8BIT = (0xb00),
325 ADC_RES_9BIT = (1 << 4),
326 ADC_RES_10BIT = (2 << 4),
327 ADC_RES_12BIT = (3 << 4),
328 ADC_RES_14BIT = (0xc00),
329 ADC_RES_16BIT = (0xd00),
330} adc_res_t;
332#endif /* ndef DOXYGEN */
333
337typedef gpio_t adc_conf_t;
338
343#define SOC_ADC_ADCCON3_EREF_INT (0 << SOC_ADC_ADCCON3_EREF_S)
344#define SOC_ADC_ADCCON3_EREF_EXT (1 << SOC_ADC_ADCCON3_EREF_S)
345#define SOC_ADC_ADCCON3_EREF_AVDD5 (2 << SOC_ADC_ADCCON3_EREF_S)
346#define SOC_ADC_ADCCON3_EREF_DIFF (3 << SOC_ADC_ADCCON3_EREF_S)
353#define SOCADC_7_BIT_RSHIFT (9U)
354#define SOCADC_9_BIT_RSHIFT (7U)
355#define SOCADC_10_BIT_RSHIFT (6U)
356#define SOCADC_12_BIT_RSHIFT (4U)
363#define RTT_DEV SMWDTHROSC
364#define RTT_IRQ SM_TIMER_ALT_IRQn
365#define RTT_IRQ_PRIO 1
366#define RTT_ISR isr_sleepmode
367#define RTT_MAX_VALUE (0xffffffff)
368#define RTT_FREQUENCY (CLOCK_OSC32K)
369/* When setting a new compare value, the value must be at least 5 more
370 than the current sleep timer value. Otherwise, the timer compare
371 event may be lost. */
372#define RTT_MIN_OFFSET (5U)
379/* Limits are in clock cycles according to data sheet.
380 As the WDT is clocked by a 32 kHz clock and supports 4 intervals */
381#define NWDT_TIME_LOWER_LIMIT (2U)
382#define NWDT_TIME_UPPER_LIMIT (1000U)
385#ifdef __cplusplus
386}
387#endif
388
389#endif /* PERIPH_CPU_H */
@ GPIO_OUT
select GPIO MASK as output
Definition periph_cpu.h:165
@ GPIO_IN
select GPIO MASK as input
Definition periph_cpu.h:164
i2c_speed_t
Definition periph_cpu.h:276
@ I2C_SPEED_NORMAL
normal mode: ~100 kbit/s
Definition periph_cpu.h:278
@ I2C_SPEED_FAST_PLUS
fast plus mode: ~1000 kbit/s
Definition periph_cpu.h:280
@ I2C_SPEED_LOW
low speed mode: ~10 kbit/s
Definition periph_cpu.h:277
@ I2C_SPEED_HIGH
high speed mode: ~3400 kbit/s
Definition periph_cpu.h:282
@ I2C_SPEED_FAST
fast mode: ~400 kbit/s
Definition periph_cpu.h:279
spi_clk_t
Definition periph_cpu.h:352
@ SPI_CLK_10MHZ
drive the SPI bus with 10MHz
Definition periph_cpu.h:357
@ SPI_CLK_5MHZ
drive the SPI bus with 5MHz
Definition periph_cpu.h:356
@ SPI_CLK_400KHZ
drive the SPI bus with 400KHz
Definition periph_cpu.h:354
@ SPI_CLK_1MHZ
drive the SPI bus with 1MHz
Definition periph_cpu.h:355
@ SPI_CLK_100KHZ
drive the SPI bus with 100KHz
Definition periph_cpu.h:353
void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over)
Configure an alternate function for the given pin.
void gpio_init_mux(gpio_t pin, uint8_t over, uint8_t sel, uint8_t func)
Configure an alternate function for the given pin.
gpio_t adc_conf_t
ADC configuration wrapper.
Definition periph_cpu.h:337
static const spi_clk_conf_t spi_clk_config[]
Pre-calculated clock divider values based on a CLOCK_CORECLOCK (32MHz)
Definition periph_cpu.h:282
adc_res_t
Possible ADC resolution settings.
Definition adc.h:93
@ ADC_RES_16BIT
ADC resolution: 16 bit.
Definition adc.h:99
@ ADC_RES_8BIT
ADC resolution: 8 bit.
Definition adc.h:95
@ ADC_RES_14BIT
ADC resolution: 14 bit.
Definition adc.h:98
@ ADC_RES_6BIT
ADC resolution: 6 bit.
Definition adc.h:94
@ ADC_RES_10BIT
ADC resolution: 10 bit.
Definition adc.h:96
@ ADC_RES_12BIT
ADC resolution: 12 bit.
Definition adc.h:97
gpio_t spi_cs_t
Chip select pin type overlaps with gpio_t so it can be casted to this.
Definition spi.h:135
spi_mode_t
Support SPI modes.
Definition periph_cpu.h:43
@ SPI_MODE_0
CPOL=0, CPHA=0.
Definition periph_cpu.h:44
@ SPI_MODE_2
CPOL=1, CPHA=0.
Definition periph_cpu.h:46
@ SPI_MODE_1
CPOL=0, CPHA=1.
Definition periph_cpu.h:45
@ SPI_MODE_3
CPOL=1, CPHA=1.
Definition periph_cpu.h:47
gpio_mode_t
Available pin modes.
Definition periph_cpu.h:82
uart_parity_t
Definition of possible parity modes.
Definition periph_cpu.h:502
@ UART_PARITY_SPACE
space parity
Definition periph_cpu.h:507
@ UART_PARITY_NONE
no parity
Definition periph_cpu.h:503
@ UART_PARITY_EVEN
even parity
Definition periph_cpu.h:504
@ UART_PARITY_ODD
odd parity
Definition periph_cpu.h:505
@ UART_PARITY_MARK
mark parity
Definition periph_cpu.h:506
uart_stop_bits_t
Definition of possible stop bits lengths.
Definition periph_cpu.h:534
@ UART_STOP_BITS_2
2 stop bits
Definition periph_cpu.h:536
@ UART_STOP_BITS_1
1 stop bit
Definition periph_cpu.h:535
uart_data_bits_t
Definition of possible data bits lengths in a UART frame.
Definition periph_cpu.h:518
@ UART_DATA_BITS_6
6 data bits
Definition periph_cpu.h:520
@ UART_DATA_BITS_5
5 data bits
Definition periph_cpu.h:519
@ UART_DATA_BITS_7
7 data bits
Definition periph_cpu.h:521
@ UART_DATA_BITS_8
8 data bits
Definition periph_cpu.h:522
stdio wrapper to extend the C libs stdio
UART component registers.
Definition cc2538_uart.h:32
I2C configuration structure.
Definition periph_cpu.h:299
Datafields for static SPI clock configuration values.
Definition periph_cpu.h:269
uint8_t cpsr
CPSR clock divider.
Definition periph_cpu.h:270
uint8_t scr
SCR clock divider.
Definition periph_cpu.h:271
SPI device configuration.
Definition periph_cpu.h:337
uint8_t num
number of SSI device, i.e.
Definition periph_cpu.h:296
spi_cs_t cs_pin
pin used for CS
Definition periph_cpu.h:300
Timer device configuration.
Definition periph_cpu.h:264
uint_fast8_t cfg
timer config word
Definition periph_cpu.h:312
uint_fast8_t chn
number of channels
Definition periph_cpu.h:311
UART device configuration.
Definition periph_cpu.h:218
cc2538_uart_t * dev
pointer to the used UART device
Definition periph_cpu.h:167