cc2538/include/periph_cpu.h
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1 /*
2  * Copyright (C) 2015-2016 Freie Universit├Ąt Berlin
3  * 2017 HAW Hamburg
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CPU_H
22 #define PERIPH_CPU_H
23 
24 #include <stdint.h>
25 #include <stdio.h>
26 
27 #include "cpu.h"
28 
29 #ifdef __cplusplus
30 extern "C" {
31 #endif
32 
36 #define CPUID_ADDR (&IEEE_ADDR_MSWORD)
37 
41 #define CPUID_LEN (8U)
42 
47 #define HAVE_GPIO_T
48 typedef uint32_t gpio_t;
55 #define PROVIDES_PM_SET_LOWEST_CORTEXM
56 
61 #define GPIO_UNDEF (0xffffffff)
62 
69 #define GPIO_PIN(port, pin) (gpio_t)(((uint32_t)GPIO_BASE + \
70  (port << GPIO_PORTNUM_SHIFT)) | pin)
71 
79 void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over);
80 
84 typedef struct {
85  gpio_t scl_pin;
86  gpio_t sda_pin;
87 } i2c_conf_t;
88 
93 #define PERIPH_SPI_NEEDS_INIT_CS
94 #define PERIPH_SPI_NEEDS_TRANSFER_BYTE
95 #define PERIPH_SPI_NEEDS_TRANSFER_REG
96 #define PERIPH_SPI_NEEDS_TRANSFER_REGS
97 
103 #define HAVE_GPIO_MODE_T
104 typedef enum {
105  GPIO_IN = ((uint8_t)OVERRIDE_DISABLE),
106  GPIO_IN_ANALOG = ((uint8_t)OVERRIDE_ANALOG),
107  GPIO_IN_PD = ((uint8_t)OVERRIDE_PULLDOWN),
108  GPIO_IN_PU = ((uint8_t)OVERRIDE_PULLUP),
109  GPIO_OUT = ((uint8_t)OVERRIDE_ENABLE),
110  GPIO_OD = (0xff),
111  GPIO_OD_PU = (0xff)
112 } gpio_mode_t;
119 #define HAVE_SPI_MODE_T
120 typedef enum {
122  SPI_MODE_1 = (SSI_CR0_SPH),
123  SPI_MODE_2 = (SSI_CR0_SPO),
124  SPI_MODE_3 = (SSI_CR0_SPO | SSI_CR0_SPH)
125 } spi_mode_t;
132 #define HAVE_SPI_CLK_T
133 typedef enum {
139 } spi_clk_t;
145 typedef struct {
146  uint8_t cpsr;
147  uint8_t scr;
149 
154 typedef struct {
156  gpio_t mosi_pin;
157  gpio_t miso_pin;
158  gpio_t sck_pin;
159  gpio_t cs_pin;
160 } spi_conf_t;
169 typedef struct {
170  uint_fast8_t chn;
171  uint_fast8_t cfg;
172 } timer_conf_t;
173 
178 #define HAVE_ADC_RES_T
179 typedef enum {
180  ADC_RES_6BIT = (0xa00),
181  ADC_RES_7BIT = (0 << 4),
182  ADC_RES_8BIT = (0xb00),
183  ADC_RES_9BIT = (1 << 4),
184  ADC_RES_10BIT = (2 << 4),
185  ADC_RES_12BIT = (3 << 4),
186  ADC_RES_14BIT = (0xc00),
187  ADC_RES_16BIT = (0xd00),
188 } adc_res_t;
194 typedef gpio_t adc_conf_t;
195 
200 #define SOC_ADC_ADCCON3_EREF (0x000000C0)
201 #define SOC_ADC_ADCCON3_EDIV (0x00000030)
202 #define SOC_ADC_ADCCON3_ECH (0x0000000F)
209 #define SOC_ADC_ADCCON_REF_INT (0 << 6)
210 #define SOC_ADC_ADCCON_REF_EXT (1 << 6)
211 #define SOC_ADC_ADCCON_REF_AVDD5 (2 << 6)
212 #define SOC_ADC_ADCCON_REF_DIFF (3 << 6)
213 #define SOC_ADC_ADCCON_CH_GND (0xC)
219 #define SOC_ADC_ADCCON1_EOC_MASK (0x80)
220 
225 #define SOC_ADC_ADCL_MASK (0x000000FC)
226 #define SOC_ADC_ADCH_MASK (0x000000FF)
227 
233 #define SOCADC_7_BIT_RSHIFT (9U)
234 #define SOCADC_9_BIT_RSHIFT (7U)
235 #define SOCADC_10_BIT_RSHIFT (6U)
236 #define SOCADC_12_BIT_RSHIFT (4U)
239 #ifdef __cplusplus
240 }
241 #endif
242 
243 #include "periph/dev_enums.h"
244 
245 #endif /* PERIPH_CPU_H */
246 
CPOL=0, CPHA=1.
ADC resolution: 7 bit.
I2C configuration options.
gpio_t cs_pin
pin used for CS
ADC resolution: 12 bit.
ADC resolution: 9 bit.
gpio_t miso_pin
pin used for MISO
gpio_t scl_pin
pin used for SCL
CPOL=0, CPHA=0.
drive the SPI bus with 100KHz
drive the SPI bus with 400KHz
uint_fast8_t cfg
timer config word
not supported by hardware
Device enumerations for backward compatibility with existing peripheral driver implementations.
ADC resolution: 10 bit.
CPOL=1, CPHA=1.
unsigned int gpio_t
GPIO type identifier.
Definition: gpio.h:69
gpio_t adc_conf_t
ADC configuration wrapper.
not supported by hardware
Datafields for static SPI clock configuration values.
gpio_t sck_pin
pin used for SCK
drive the SPI bus with 5MHz
not supported by hardware
uint_fast8_t chn
number of channels
not supported by hardware
drive the SPI bus with 10MHz
drive the SPI bus with 1MHz
void gpio_init_af(gpio_t pin, uint8_t sel, uint8_t over)
Configure an alternate function for the given pin.
stdio.h wrapper for MSP430
input, no pull
uint8_t scr
SCR clock divider.
not supported
gpio_t sda_pin
pin used for SDA
CPOL=1, CPHA=0.
SPI module configuration options.
input, pull-down
uint8_t cpsr
CPSR clock divider.
Timer configuration.
gpio_t mosi_pin
pin used for MOSI
SSI component registers.
Definition: cc2538_ssi.h:31
cc2538_ssi_t * dev
SSI device.