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periph_conf.h
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1/*
2 * Copyright (C) 2018 Inria
3 *
4 * This file is subject to the terms and conditions of the GNU Lesser
5 * General Public License v2.1. See the file LICENSE in the top level
6 * directory for more details.
7 */
8
19#ifndef PERIPH_CONF_H
20#define PERIPH_CONF_H
21
22/* Add specific clock configuration (HSE, LSE) for this board here */
23#ifndef CONFIG_BOARD_HAS_LSE
24#define CONFIG_BOARD_HAS_LSE 1
25#endif
26
27#include "periph_cpu.h"
28#include "clk_conf.h"
29#include "cfg_rtt_default.h"
30#include "cfg_usb_otg_fs.h"
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
40static const timer_conf_t timer_config[] = {
41 {
42 .dev = TIM5,
43 .max = 0xffffffff,
44 .rcc_mask = RCC_APB1ENR1_TIM5EN,
45 .bus = APB1,
46 .irqn = TIM5_IRQn
47 }
48};
49
50#define TIMER_0_ISR isr_tim5
51
52#define TIMER_NUMOF ARRAY_SIZE(timer_config)
59static const uart_conf_t uart_config[] = {
60 {
61 .dev = USART2,
62 .rcc_mask = RCC_APB1ENR1_USART2EN,
63 .rx_pin = GPIO_PIN(PORT_D, 6),
64 .tx_pin = GPIO_PIN(PORT_D, 5),
65 .rx_af = GPIO_AF7,
66 .tx_af = GPIO_AF7,
67 .bus = APB1,
68 .irqn = USART2_IRQn,
69 .type = STM32_USART,
70 .clk_src = 0, /* Use APB clock */
71#ifdef UART_USE_DMA
72 .dma_stream = 6,
73 .dma_chan = 4
74#endif
75 }
76};
77
78#define UART_0_ISR (isr_usart2)
79
80#define UART_NUMOF ARRAY_SIZE(uart_config)
83#ifdef __cplusplus
84}
85#endif
86
87#endif /* PERIPH_CONF_H */
@ PORT_D
port D
Definition periph_cpu.h:50
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
Common configuration for STM32 OTG FS peripheral.
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:38
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
Timer device configuration.
Definition periph_cpu.h:264
TC0_t * dev
Pointer to the used as Timer device.
Definition periph_cpu.h:265
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219