periph_conf.h File Reference

Peripheral MCU configuration for the STM32L0538-DISCO board. More...

Detailed Description

Peripheral MCU configuration for the STM32L0538-DISCO board.

Author
Alexandre Abadie alexa.nosp@m.ndre.nosp@m..abad.nosp@m.ie@i.nosp@m.nria..nosp@m.fr

Definition in file periph_conf.h.

#include "periph_cpu.h"
+ Include dependency graph for periph_conf.h:

Go to the source code of this file.

Clock system configuration

#define CLOCK_HSI   (16000000U) /* internal oscillator */
 
#define CLOCK_CORECLOCK   (32000000U) /* desired core clock frequency */
 
#define CLOCK_LSE   (0) /* enable low speed external oscillator */
 
#define CLOCK_PLL_DIV   RCC_CFGR_PLLDIV2
 
#define CLOCK_PLL_MUL   RCC_CFGR_PLLMUL4
 
#define CLOCK_AHB_DIV   RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
 
#define CLOCK_APB2_DIV   RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
 
#define CLOCK_APB1_DIV   RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
 
#define CLOCK_FLASH_LATENCY   FLASH_ACR_LATENCY
 
#define CLOCK_AHB   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB2   (CLOCK_CORECLOCK / 1)
 
#define CLOCK_APB1   (CLOCK_CORECLOCK / 1)
 

Timer configuration

#define TIMER_0_ISR   isr_tim2
 
#define TIMER_NUMOF   ARRAY_SIZE(timer_config)
 
static const timer_conf_t timer_config []
 

UART configuration

#define UART_0_ISR   (isr_usart1)
 
#define UART_NUMOF   ARRAY_SIZE(uart_config)
 
static const uart_conf_t uart_config []
 

SPI configuration

Note
The spi_divtable is auto-generated from cpu/stm32_common/dist/spi_divtable/spi_divtable.c
#define SPI_NUMOF   ARRAY_SIZE(spi_config)
 
static const uint8_t spi_divtable [2][5]
 
static const spi_conf_t spi_config []
 

Variable Documentation

◆ spi_config

const spi_conf_t spi_config[]
static
Initial value:
= {
{
.dev = SPI1,
.mosi_pin = GPIO_PIN(PORT_B, 5),
.miso_pin = GPIO_PIN(PORT_B, 4),
.sclk_pin = GPIO_PIN(PORT_B, 3),
.cs_pin = GPIO_UNDEF,
.af = GPIO_AF0,
.rccmask = RCC_APB2ENR_SPI1EN,
.apbbus = APB2
},
{
.dev = SPI2,
.mosi_pin = GPIO_PIN(PORT_B, 15),
.miso_pin = GPIO_PIN(PORT_B, 14),
.sclk_pin = GPIO_PIN(PORT_B, 13),
.cs_pin = GPIO_PIN(PORT_B, 12),
.af = GPIO_AF0,
.rccmask = RCC_APB1ENR_SPI2EN,
.apbbus = APB1
},
}
APB1 bus.
use alternate function 0
APB2 bus.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
port B
Definition: periph_cpu.h:37

Definition at line 120 of file periph_conf.h.

◆ spi_divtable

const uint8_t spi_divtable[2][5]
static
Initial value:
= {
{
7,
5,
4,
2,
1
},
{
7,
5,
4,
2,
1
}
}

Definition at line 103 of file periph_conf.h.

◆ timer_config

const timer_conf_t timer_config[]
static
Initial value:
= {
{
.dev = TIM2,
.max = 0x0000ffff,
.rcc_mask = RCC_APB1ENR_TIM2EN,
.bus = APB1,
.irqn = TIM2_IRQn
}
}
APB1 bus.

Definition at line 57 of file periph_conf.h.

◆ uart_config

const uart_conf_t uart_config[]
static
Initial value:
= {
{
.dev = USART1,
.rcc_mask = RCC_APB2ENR_USART1EN,
.rx_pin = GPIO_PIN(PORT_A, 10),
.tx_pin = GPIO_PIN(PORT_A, 9),
.rx_af = GPIO_AF4,
.tx_af = GPIO_AF4,
.bus = APB2,
.irqn = USART1_IRQn,
.type = STM32_USART,
.clk_src = 0,
}
}
use alternate function 4
STM32 USART module type.
port A
Definition: periph_cpu.h:36
APB2 bus.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35

Definition at line 76 of file periph_conf.h.