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boards/stm32f4discovery/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 #define CLOCK_HSE (8000000U) /* external oscillator */
34 #define CLOCK_CORECLOCK (168000000U) /* desired core clock frequency */
35 
36 /* the actual PLL values are automatically generated */
37 #define CLOCK_PLL_M (CLOCK_HSE / 1000000)
38 #define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
39 #define CLOCK_PLL_P (2U)
40 #define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
41 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
42 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
43 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
44 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
45 
46 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
47 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
48 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
49 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
50 
56 static const timer_conf_t timer_config[] = {
57  {
58  .dev = TIM2,
59  .max = 0xffffffff,
60  .rcc_mask = RCC_APB1ENR_TIM2EN,
61  .bus = APB1,
62  .irqn = TIM2_IRQn
63  },
64  {
65  .dev = TIM5,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM5EN,
68  .bus = APB1,
69  .irqn = TIM5_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim2
74 #define TIMER_1_ISR isr_tim5
75 
76 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
77 
83 static const uart_conf_t uart_config[] = {
84  {
85  .dev = USART2,
86  .rcc_mask = RCC_APB1ENR_USART2EN,
87  .rx_pin = GPIO_PIN(PORT_A, 3),
88  .tx_pin = GPIO_PIN(PORT_A, 2),
89  .rx_af = GPIO_AF7,
90  .tx_af = GPIO_AF7,
91  .bus = APB1,
92  .irqn = USART2_IRQn,
93 #ifdef UART_USE_DMA
94  .dma_stream = 6,
95  .dma_chan = 4
96 #endif
97  },
98  {
99  .dev = USART3,
100  .rcc_mask = RCC_APB1ENR_USART3EN,
101  .rx_pin = GPIO_PIN(PORT_D, 9),
102  .tx_pin = GPIO_PIN(PORT_D, 8),
103  .rx_af = GPIO_AF7,
104  .tx_af = GPIO_AF7,
105  .bus = APB1,
106  .irqn = USART3_IRQn,
107 #ifdef UART_USE_DMA
108  .dma_stream = 3,
109  .dma_chan = 4
110 #endif
111  }
112 };
113 
114 #define UART_0_ISR (isr_usart2)
115 #define UART_0_DMA_ISR (isr_dma1_stream6)
116 #define UART_1_ISR (isr_usart3)
117 #define UART_1_DMA_ISR (isr_dma1_stream3)
118 
119 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
120 
129 #define ADC_CONFIG { \
130  {GPIO_PIN(PORT_A, 1), 0, 1}, \
131  {GPIO_PIN(PORT_A, 4), 0, 4}, \
132  {GPIO_PIN(PORT_C, 1), 1, 11}, \
133  {GPIO_PIN(PORT_C, 2), 1, 12} \
134 }
135 
136 #define ADC_NUMOF (4)
137 
146 #define DAC_CONFIG { \
147  { GPIO_PIN(PORT_A, 4), 0 }, \
148  { GPIO_PIN(PORT_A, 5), 1 }, \
149 }
150 
151 #define DAC_NUMOF (2)
152 
158 static const pwm_conf_t pwm_config[] = {
159  {
160  .dev = TIM1,
161  .rcc_mask = RCC_APB2ENR_TIM1EN,
162  .chan = { { .pin = GPIO_PIN(PORT_E, 9), .cc_chan = 0 },
163  { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 1 },
164  { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 2 },
165  { .pin = GPIO_PIN(PORT_E, 14), .cc_chan = 3 } },
166  .af = GPIO_AF1,
167  .bus = APB2
168  },
169  {
170  .dev = TIM3,
171  .rcc_mask = RCC_APB1ENR_TIM3EN,
172  .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
173  { .pin = GPIO_PIN(PORT_B, 5), .cc_chan = 1 },
174  { .pin = GPIO_PIN(PORT_B, 0), .cc_chan = 2 },
175  { .pin = GPIO_PIN(PORT_B, 1), .cc_chan = 3 } },
176  .af = GPIO_AF2,
177  .bus = APB1
178  }
179 };
180 
181 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
182 
191 static const uint8_t spi_divtable[2][5] = {
192  { /* for APB1 @ 42000000Hz */
193  7, /* -> 164062Hz */
194  6, /* -> 328125Hz */
195  4, /* -> 1312500Hz */
196  2, /* -> 5250000Hz */
197  1 /* -> 10500000Hz */
198  },
199  { /* for APB2 @ 84000000Hz */
200  7, /* -> 328125Hz */
201  7, /* -> 328125Hz */
202  5, /* -> 1312500Hz */
203  3, /* -> 5250000Hz */
204  2 /* -> 10500000Hz */
205  }
206 };
207 
208 static const spi_conf_t spi_config[] = {
209  {
210  .dev = SPI1,
211  .mosi_pin = GPIO_PIN(PORT_A, 7),
212  .miso_pin = GPIO_PIN(PORT_A, 6),
213  .sclk_pin = GPIO_PIN(PORT_A, 5),
214  .cs_pin = GPIO_PIN(PORT_A, 4),
215  .af = GPIO_AF5,
216  .rccmask = RCC_APB2ENR_SPI1EN,
217  .apbbus = APB2
218  },
219  {
220  .dev = SPI2,
221  .mosi_pin = GPIO_PIN(PORT_B, 15),
222  .miso_pin = GPIO_PIN(PORT_B, 14),
223  .sclk_pin = GPIO_PIN(PORT_B, 13),
224  .cs_pin = GPIO_PIN(PORT_B, 12),
225  .af = GPIO_AF5,
226  .rccmask = RCC_APB1ENR_SPI2EN,
227  .apbbus = APB1
228  }
229 };
230 
231 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
232 
238 #define I2C_NUMOF (1U)
239 #define I2C_0_EN 1
240 #define I2C_IRQ_PRIO 1
241 #define I2C_APBCLK (42000000U)
242 
243 /* I2C 0 device configuration */
244 #define I2C_0_DEV I2C1
245 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
246 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
247 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
248 #define I2C_0_EVT_ISR isr_i2c1_ev
249 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
250 #define I2C_0_ERR_ISR isr_i2c1_er
251 /* I2C 0 pin configuration */
252 #define I2C_0_SCL_PORT GPIOB
253 #define I2C_0_SCL_PIN 6
254 #define I2C_0_SCL_AF 4
255 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
256 #define I2C_0_SDA_PORT GPIOB
257 #define I2C_0_SDA_PIN 7
258 #define I2C_0_SDA_AF 4
259 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
260 
262 #ifdef __cplusplus
263 }
264 #endif
265 
266 #endif /* PERIPH_CONF_H */
267 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.