boards/stm32f4discovery/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
36 /* give the target core clock (HCLK) frequency [in Hz],
37  * maximum: 168MHz */
38 #define CLOCK_CORECLOCK (168000000U)
39 /* 0: no external high speed crystal available
40  * else: actual crystal frequency [in Hz] */
41 #define CLOCK_HSE (8000000U)
42 /* 0: no external low speed crystal available,
43  * 1: external crystal available (always 32.768kHz) */
44 #define CLOCK_LSE (1)
45 /* peripheral clock setup */
46 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
47 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
48 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
49 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
50 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
51 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
52 
53 /* Main PLL factors */
54 #define CLOCK_PLL_M (4)
55 #define CLOCK_PLL_N (168)
56 #define CLOCK_PLL_P (2)
57 #define CLOCK_PLL_Q (7)
58 
64 static const timer_conf_t timer_config[] = {
65  {
66  .dev = TIM2,
67  .max = 0xffffffff,
68  .rcc_mask = RCC_APB1ENR_TIM2EN,
69  .bus = APB1,
70  .irqn = TIM2_IRQn
71  },
72  {
73  .dev = TIM5,
74  .max = 0xffffffff,
75  .rcc_mask = RCC_APB1ENR_TIM5EN,
76  .bus = APB1,
77  .irqn = TIM5_IRQn
78  }
79 };
80 
81 #define TIMER_0_ISR isr_tim2
82 #define TIMER_1_ISR isr_tim5
83 
84 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
85 
91 static const uart_conf_t uart_config[] = {
92  {
93  .dev = USART2,
94  .rcc_mask = RCC_APB1ENR_USART2EN,
95  .rx_pin = GPIO_PIN(PORT_A, 3),
96  .tx_pin = GPIO_PIN(PORT_A, 2),
97  .rx_af = GPIO_AF7,
98  .tx_af = GPIO_AF7,
99  .bus = APB1,
100  .irqn = USART2_IRQn,
101 #ifdef UART_USE_DMA
102  .dma_stream = 6,
103  .dma_chan = 4
104 #endif
105  },
106  {
107  .dev = USART3,
108  .rcc_mask = RCC_APB1ENR_USART3EN,
109  .rx_pin = GPIO_PIN(PORT_D, 9),
110  .tx_pin = GPIO_PIN(PORT_D, 8),
111  .rx_af = GPIO_AF7,
112  .tx_af = GPIO_AF7,
113  .bus = APB1,
114  .irqn = USART3_IRQn,
115 #ifdef UART_USE_DMA
116  .dma_stream = 3,
117  .dma_chan = 4
118 #endif
119  }
120 };
121 
122 #define UART_0_ISR (isr_usart2)
123 #define UART_0_DMA_ISR (isr_dma1_stream6)
124 #define UART_1_ISR (isr_usart3)
125 #define UART_1_DMA_ISR (isr_dma1_stream3)
126 
127 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
128 
137 #define ADC_CONFIG { \
138  {GPIO_PIN(PORT_A, 1), 0, 1}, \
139  {GPIO_PIN(PORT_A, 4), 0, 4}, \
140  {GPIO_PIN(PORT_C, 1), 1, 11}, \
141  {GPIO_PIN(PORT_C, 2), 1, 12} \
142 }
143 
144 #define ADC_NUMOF (4)
145 
151 static const dac_conf_t dac_config[] = {
152  { .pin = GPIO_PIN(PORT_A, 4), .chan = 0 },
153  { .pin = GPIO_PIN(PORT_A, 5), .chan = 1 }
154 };
155 
156 #define DAC_NUMOF (sizeof(dac_config) / sizeof(dac_config[0]))
157 
163 static const pwm_conf_t pwm_config[] = {
164  {
165  .dev = TIM1,
166  .rcc_mask = RCC_APB2ENR_TIM1EN,
167  .chan = { { .pin = GPIO_PIN(PORT_E, 9), .cc_chan = 0 },
168  { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 1 },
169  { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 2 },
170  { .pin = GPIO_PIN(PORT_E, 14), .cc_chan = 3 } },
171  .af = GPIO_AF1,
172  .bus = APB2
173  },
174  {
175  .dev = TIM3,
176  .rcc_mask = RCC_APB1ENR_TIM3EN,
177  .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
178  { .pin = GPIO_PIN(PORT_B, 5), .cc_chan = 1 },
179  { .pin = GPIO_PIN(PORT_B, 0), .cc_chan = 2 },
180  { .pin = GPIO_PIN(PORT_B, 1), .cc_chan = 3 } },
181  .af = GPIO_AF2,
182  .bus = APB1
183  }
184 };
185 
186 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
187 
196 static const uint8_t spi_divtable[2][5] = {
197  { /* for APB1 @ 42000000Hz */
198  7, /* -> 164062Hz */
199  6, /* -> 328125Hz */
200  4, /* -> 1312500Hz */
201  2, /* -> 5250000Hz */
202  1 /* -> 10500000Hz */
203  },
204  { /* for APB2 @ 84000000Hz */
205  7, /* -> 328125Hz */
206  7, /* -> 328125Hz */
207  5, /* -> 1312500Hz */
208  3, /* -> 5250000Hz */
209  2 /* -> 10500000Hz */
210  }
211 };
212 
213 static const spi_conf_t spi_config[] = {
214  {
215  .dev = SPI1,
216  .mosi_pin = GPIO_PIN(PORT_A, 7),
217  .miso_pin = GPIO_PIN(PORT_A, 6),
218  .sclk_pin = GPIO_PIN(PORT_A, 5),
219  .cs_pin = GPIO_PIN(PORT_A, 4),
220  .af = GPIO_AF5,
221  .rccmask = RCC_APB2ENR_SPI1EN,
222  .apbbus = APB2
223  },
224  {
225  .dev = SPI2,
226  .mosi_pin = GPIO_PIN(PORT_B, 15),
227  .miso_pin = GPIO_PIN(PORT_B, 14),
228  .sclk_pin = GPIO_PIN(PORT_B, 13),
229  .cs_pin = GPIO_PIN(PORT_B, 12),
230  .af = GPIO_AF5,
231  .rccmask = RCC_APB1ENR_SPI2EN,
232  .apbbus = APB1
233  }
234 };
235 
236 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
237 
243 #define I2C_NUMOF (1U)
244 #define I2C_0_EN 1
245 #define I2C_IRQ_PRIO 1
246 #define I2C_APBCLK (CLOCK_APB1)
247 
248 /* I2C 0 device configuration */
249 #define I2C_0_DEV I2C1
250 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
251 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
252 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
253 #define I2C_0_EVT_ISR isr_i2c1_ev
254 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
255 #define I2C_0_ERR_ISR isr_i2c1_er
256 /* I2C 0 pin configuration */
257 #define I2C_0_SCL_PORT GPIOB
258 #define I2C_0_SCL_PIN 6
259 #define I2C_0_SCL_AF 4
260 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
261 #define I2C_0_SDA_PORT GPIOB
262 #define I2C_0_SDA_PIN 7
263 #define I2C_0_SDA_AF 4
264 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
265 
267 #ifdef __cplusplus
268 }
269 #endif
270 
271 #endif /* PERIPH_CONF_H */
272 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
gpio_t pin
pin connected to the line
use alternate function 1
PWM configuration structure.
NRF_TIMER_Type * dev
timer device
use alternate function 5
Tcc * dev
TCC device to use.
UART device configuration.
DAC line configuration data.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.