boards/stm32f4discovery/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 /* 0: no external high speed crystal available
34  * else: actual crystal frequency [in Hz] */
35 #define CLOCK_HSE (8000000U)
36 /* 0: no external low speed crystal available,
37  * 1: external crystal available (always 32.768kHz) */
38 #define CLOCK_LSE (1)
39 /* give the target core clock (HCLK) frequency [in Hz],
40  * maximum: 168MHz */
41 #define CLOCK_CORECLOCK (168000000U)
42 /* peripheral clock setup */
43 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
44 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
45 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
46 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
47 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
48 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
49 
55 static const timer_conf_t timer_config[] = {
56  {
57  .dev = TIM2,
58  .max = 0xffffffff,
59  .rcc_mask = RCC_APB1ENR_TIM2EN,
60  .bus = APB1,
61  .irqn = TIM2_IRQn
62  },
63  {
64  .dev = TIM5,
65  .max = 0xffffffff,
66  .rcc_mask = RCC_APB1ENR_TIM5EN,
67  .bus = APB1,
68  .irqn = TIM5_IRQn
69  }
70 };
71 
72 #define TIMER_0_ISR isr_tim2
73 #define TIMER_1_ISR isr_tim5
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART2,
85  .rcc_mask = RCC_APB1ENR_USART2EN,
86  .rx_pin = GPIO_PIN(PORT_A, 3),
87  .tx_pin = GPIO_PIN(PORT_A, 2),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB1,
91  .irqn = USART2_IRQn,
92 #ifdef UART_USE_DMA
93  .dma_stream = 6,
94  .dma_chan = 4
95 #endif
96  },
97  {
98  .dev = USART3,
99  .rcc_mask = RCC_APB1ENR_USART3EN,
100  .rx_pin = GPIO_PIN(PORT_D, 9),
101  .tx_pin = GPIO_PIN(PORT_D, 8),
102  .rx_af = GPIO_AF7,
103  .tx_af = GPIO_AF7,
104  .bus = APB1,
105  .irqn = USART3_IRQn,
106 #ifdef UART_USE_DMA
107  .dma_stream = 3,
108  .dma_chan = 4
109 #endif
110  }
111 };
112 
113 #define UART_0_ISR (isr_usart2)
114 #define UART_0_DMA_ISR (isr_dma1_stream6)
115 #define UART_1_ISR (isr_usart3)
116 #define UART_1_DMA_ISR (isr_dma1_stream3)
117 
118 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
119 
128 #define ADC_CONFIG { \
129  {GPIO_PIN(PORT_A, 1), 0, 1}, \
130  {GPIO_PIN(PORT_A, 4), 0, 4}, \
131  {GPIO_PIN(PORT_C, 1), 1, 11}, \
132  {GPIO_PIN(PORT_C, 2), 1, 12} \
133 }
134 
135 #define ADC_NUMOF (4)
136 
145 #define DAC_CONFIG { \
146  { GPIO_PIN(PORT_A, 4), 0 }, \
147  { GPIO_PIN(PORT_A, 5), 1 }, \
148 }
149 
150 #define DAC_NUMOF (2)
151 
157 static const pwm_conf_t pwm_config[] = {
158  {
159  .dev = TIM1,
160  .rcc_mask = RCC_APB2ENR_TIM1EN,
161  .chan = { { .pin = GPIO_PIN(PORT_E, 9), .cc_chan = 0 },
162  { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 1 },
163  { .pin = GPIO_PIN(PORT_E, 11), .cc_chan = 2 },
164  { .pin = GPIO_PIN(PORT_E, 14), .cc_chan = 3 } },
165  .af = GPIO_AF1,
166  .bus = APB2
167  },
168  {
169  .dev = TIM3,
170  .rcc_mask = RCC_APB1ENR_TIM3EN,
171  .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
172  { .pin = GPIO_PIN(PORT_B, 5), .cc_chan = 1 },
173  { .pin = GPIO_PIN(PORT_B, 0), .cc_chan = 2 },
174  { .pin = GPIO_PIN(PORT_B, 1), .cc_chan = 3 } },
175  .af = GPIO_AF2,
176  .bus = APB1
177  }
178 };
179 
180 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
181 
190 static const uint8_t spi_divtable[2][5] = {
191  { /* for APB1 @ 42000000Hz */
192  7, /* -> 164062Hz */
193  6, /* -> 328125Hz */
194  4, /* -> 1312500Hz */
195  2, /* -> 5250000Hz */
196  1 /* -> 10500000Hz */
197  },
198  { /* for APB2 @ 84000000Hz */
199  7, /* -> 328125Hz */
200  7, /* -> 328125Hz */
201  5, /* -> 1312500Hz */
202  3, /* -> 5250000Hz */
203  2 /* -> 10500000Hz */
204  }
205 };
206 
207 static const spi_conf_t spi_config[] = {
208  {
209  .dev = SPI1,
210  .mosi_pin = GPIO_PIN(PORT_A, 7),
211  .miso_pin = GPIO_PIN(PORT_A, 6),
212  .sclk_pin = GPIO_PIN(PORT_A, 5),
213  .cs_pin = GPIO_PIN(PORT_A, 4),
214  .af = GPIO_AF5,
215  .rccmask = RCC_APB2ENR_SPI1EN,
216  .apbbus = APB2
217  },
218  {
219  .dev = SPI2,
220  .mosi_pin = GPIO_PIN(PORT_B, 15),
221  .miso_pin = GPIO_PIN(PORT_B, 14),
222  .sclk_pin = GPIO_PIN(PORT_B, 13),
223  .cs_pin = GPIO_PIN(PORT_B, 12),
224  .af = GPIO_AF5,
225  .rccmask = RCC_APB1ENR_SPI2EN,
226  .apbbus = APB1
227  }
228 };
229 
230 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
231 
237 #define I2C_NUMOF (1U)
238 #define I2C_0_EN 1
239 #define I2C_IRQ_PRIO 1
240 #define I2C_APBCLK (CLOCK_APB1)
241 
242 /* I2C 0 device configuration */
243 #define I2C_0_DEV I2C1
244 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
245 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
246 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
247 #define I2C_0_EVT_ISR isr_i2c1_ev
248 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
249 #define I2C_0_ERR_ISR isr_i2c1_er
250 /* I2C 0 pin configuration */
251 #define I2C_0_SCL_PORT GPIOB
252 #define I2C_0_SCL_PIN 6
253 #define I2C_0_SCL_AF 4
254 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
255 #define I2C_0_SDA_PORT GPIOB
256 #define I2C_0_SDA_PIN 7
257 #define I2C_0_SDA_AF 4
258 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
259 
261 #ifdef __cplusplus
262 }
263 #endif
264 
265 #endif /* PERIPH_CONF_H */
266 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.