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boards/stm32f3discovery/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLOCK_HSE (8000000U) /* external oscillator */
33 #define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
34 
35 /* the actual PLL values are automatically generated */
36 #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
37 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
38 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
39 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
40 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
41 
42 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
43 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
44 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
45 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
46 
52 #define DAC_CONFIG { \
53  { GPIO_PIN(PORT_A, 4), 0, 0 }, \
54 }
55 
56 #define DAC_NUMOF (1)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM2,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM2EN,
68  .bus = APB1,
69  .irqn = TIM2_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim2
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART1,
85  .rcc_mask = RCC_APB2ENR_USART1EN,
86  .rx_pin = GPIO_PIN(PORT_A, 10),
87  .tx_pin = GPIO_PIN(PORT_A, 9),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB2,
91  .irqn = USART1_IRQn
92  },
93  {
94  .dev = USART2,
95  .rcc_mask = RCC_APB1ENR_USART2EN,
96  .rx_pin = GPIO_PIN(PORT_D, 6),
97  .tx_pin = GPIO_PIN(PORT_D, 5),
98  .rx_af = GPIO_AF7,
99  .tx_af = GPIO_AF7,
100  .bus = APB1,
101  .irqn = USART2_IRQn
102  },
103  {
104  .dev = USART3,
105  .rcc_mask = RCC_APB1ENR_USART3EN,
106  .rx_pin = GPIO_PIN(PORT_D, 9),
107  .tx_pin = GPIO_PIN(PORT_D, 8),
108  .rx_af = GPIO_AF7,
109  .tx_af = GPIO_AF7,
110  .bus = APB1,
111  .irqn = USART3_IRQn
112  }
113 };
114 
115 #define UART_0_ISR (isr_usart1)
116 #define UART_1_ISR (isr_usart2)
117 #define UART_2_ISR (isr_usart3)
118 
119 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
120 
126 static const pwm_conf_t pwm_config[] = {
127  {
128  .dev = TIM3,
129  .rcc_mask = RCC_APB1ENR_TIM3EN,
130  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
131  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
132  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
133  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
134  .af = GPIO_AF2,
135  .bus = APB1
136  },
137  {
138  .dev = TIM4,
139  .rcc_mask = RCC_APB1ENR_TIM4EN,
140  .chan = { { .pin = GPIO_PIN(PORT_D, 12), .cc_chan = 0},
141  { .pin = GPIO_PIN(PORT_D, 13), .cc_chan = 1},
142  { .pin = GPIO_PIN(PORT_D, 14), .cc_chan = 2},
143  { .pin = GPIO_PIN(PORT_D, 15), .cc_chan = 3} },
144  .af = GPIO_AF2,
145  .bus = APB1
146  }
147 };
148 
149 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
150 
156 static const uint8_t spi_divtable[2][5] = {
157  { /* for APB1 @ 36000000Hz */
158  7, /* -> 140625Hz */
159  6, /* -> 281250Hz */
160  4, /* -> 1125000Hz */
161  2, /* -> 4500000Hz */
162  1 /* -> 9000000Hz */
163  },
164  { /* for APB2 @ 72000000Hz */
165  7, /* -> 281250Hz */
166  7, /* -> 281250Hz */
167  5, /* -> 1125000Hz */
168  3, /* -> 4500000Hz */
169  2 /* -> 9000000Hz */
170  }
171 };
172 
173 static const spi_conf_t spi_config[] = {
174  {
175  .dev = SPI1,
176  .mosi_pin = GPIO_PIN(PORT_A, 7),
177  .miso_pin = GPIO_PIN(PORT_A, 6),
178  .sclk_pin = GPIO_PIN(PORT_A, 5),
179  .cs_pin = GPIO_UNDEF,
180  .af = GPIO_AF5,
181  .rccmask = RCC_APB2ENR_SPI1EN,
182  .apbbus = APB2
183  },
184  {
185  .dev = SPI3,
186  .mosi_pin = GPIO_PIN(PORT_C, 12),
187  .miso_pin = GPIO_PIN(PORT_C, 11),
188  .sclk_pin = GPIO_PIN(PORT_C, 10),
189  .cs_pin = GPIO_PIN(PORT_A, 15),
190  .af = GPIO_AF6,
191  .rccmask = RCC_APB1ENR_SPI3EN,
192  .apbbus = APB1
193  }
194 };
195 
196 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
197 
203 #define I2C_NUMOF (2U)
204 #define I2C_0_EN 1
205 #define I2C_1_EN 1
206 #define I2C_IRQ_PRIO 1
207 #define I2C_APBCLK (36000000U)
208 
209 /* I2C 0 device configuration */
210 #define I2C_0_DEV I2C1
211 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
212 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
213 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
214 #define I2C_0_EVT_ISR isr_i2c1_ev
215 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
216 #define I2C_0_ERR_ISR isr_i2c1_er
217 /* I2C 0 pin configuration */
218 #define I2C_0_SCL_PORT GPIOB
219 #define I2C_0_SCL_PIN 6
220 #define I2C_0_SCL_AF 4
221 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
222 #define I2C_0_SDA_PORT GPIOB
223 #define I2C_0_SDA_PIN 7
224 #define I2C_0_SDA_AF 4
225 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOBEN))
226 
227 /* I2C 1 device configuration */
228 #define I2C_1_DEV I2C2
229 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C2EN))
230 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C2EN))
231 #define I2C_1_EVT_IRQ I2C2_EV_IRQn
232 #define I2C_1_EVT_ISR isr_i2c2_ev
233 #define I2C_1_ERR_IRQ I2C2_ER_IRQn
234 #define I2C_1_ERR_ISR isr_i2c2_er
235 /* I2C 1 pin configuration */
236 #define I2C_1_SCL_PORT GPIOF
237 #define I2C_1_SCL_PIN 1
238 #define I2C_1_SCL_AF 4
239 #define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOFEN))
240 #define I2C_1_SDA_PORT GPIOF
241 #define I2C_1_SDA_PIN 0
242 #define I2C_1_SDA_AF 4
243 #define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_AHBENR_GPIOFEN))
244 
246 #ifdef __cplusplus
247 }
248 #endif
249 
250 #endif /* PERIPH_CONF_H */
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 6
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.