boards/stm32f0discovery/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 48MHz */
37 #define CLOCK_CORECLOCK (48000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (8000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (0)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB2 (CLOCK_APB1)
50 
51 /* PLL factors */
52 #define CLOCK_PLL_PREDIV (1)
53 #define CLOCK_PLL_MUL (6)
54 
60 static const timer_conf_t timer_config[] = {
61  {
62  .dev = TIM2,
63  .max = 0xffffffff,
64  .rcc_mask = RCC_APB1ENR_TIM2EN,
65  .bus = APB1,
66  .irqn = TIM2_IRQn
67  }
68 };
69 
70 #define TIMER_0_ISR isr_tim2
71 
72 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
73 
79 static const uart_conf_t uart_config[] = {
80  {
81  .dev = USART1,
82  .rcc_mask = RCC_APB2ENR_USART1EN,
83  .rx_pin = GPIO_PIN(PORT_B, 7),
84  .tx_pin = GPIO_PIN(PORT_B, 6),
85  .rx_af = GPIO_AF0,
86  .tx_af = GPIO_AF0,
87  .bus = APB2,
88  .irqn = USART1_IRQn,
89  },
90  {
91  .dev = USART2,
92  .rcc_mask = RCC_APB1ENR_USART2EN,
93  .rx_pin = GPIO_PIN(PORT_A, 3),
94  .tx_pin = GPIO_PIN(PORT_A, 2),
95  .rx_af = GPIO_AF1,
96  .tx_af = GPIO_AF1,
97  .bus = APB1,
98  .irqn = USART2_IRQn
99  }
100 };
101 
102 #define UART_0_ISR (isr_usart1)
103 #define UART_1_ISR (isr_usart2)
104 
105 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
106 
115 #define ADC_CONFIG { \
116  { GPIO_PIN(PORT_C, 0), 10 },\
117  { GPIO_PIN(PORT_C, 1), 11 },\
118  { GPIO_PIN(PORT_C, 2), 12 },\
119  { GPIO_PIN(PORT_C, 3), 13 },\
120  { GPIO_PIN(PORT_C, 4), 14 },\
121  { GPIO_PIN(PORT_C, 5), 15 } \
122 }
123 
124 #define ADC_NUMOF (6)
125 
131 static const uint8_t spi_divtable[2][5] = {
132  { /* for APB1 @ 48000000Hz */
133  7, /* -> 187500Hz */
134  6, /* -> 375000Hz */
135  5, /* -> 750000Hz */
136  2, /* -> 6000000Hz */
137  1 /* -> 12000000Hz */
138  },
139  { /* for APB2 @ 48000000Hz */
140  7, /* -> 187500Hz */
141  6, /* -> 375000Hz */
142  5, /* -> 750000Hz */
143  2, /* -> 6000000Hz */
144  1 /* -> 12000000Hz */
145  }
146 };
147 
148 static const spi_conf_t spi_config[] = {
149  {
150  .dev = SPI1,
151  .mosi_pin = GPIO_PIN(PORT_A, 7),
152  .miso_pin = GPIO_PIN(PORT_A, 6),
153  .sclk_pin = GPIO_PIN(PORT_A, 5),
154  .cs_pin = GPIO_UNDEF,
155  .af = GPIO_AF0,
156  .rccmask = RCC_APB2ENR_SPI1EN,
157  .apbbus = APB2
158  },
159  {
160  .dev = SPI2,
161  .mosi_pin = GPIO_PIN(PORT_B, 15),
162  .miso_pin = GPIO_PIN(PORT_B, 14),
163  .sclk_pin = GPIO_PIN(PORT_B, 13),
164  .cs_pin = GPIO_UNDEF,
165  .af = GPIO_AF0,
166  .rccmask = RCC_APB1ENR_SPI2EN,
167  .apbbus = APB1
168  }
169 };
170 
171 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
172 
174 #ifdef __cplusplus
175 }
176 #endif
177 
178 #endif /* PERIPH_CONF_H */
void * dev
UART, USART or LEUART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
NRF_TIMER_Type * dev
timer device
use alternate function 0
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
cc2538_ssi_t * dev
SSI device.