boards/spark-core/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
32 /* high speed clock configuration:
33  * 0 := use internal HSI oscillator (always 8MHz)
34  * HSE frequency value := use external HSE oscillator with given freq [in Hz]
35  * must be 4000000 <= value <= 16000000 */
36 #define CLOCK_HSE (8000000U)
37 /* low speed clock configuration:
38  * 0 := use internal LSI oscillator (~40kHz)
39  * 1 := use extern LSE oscillator, always 32.768kHz */
40 #define CLOCK_LSE (0)
41 /* targeted system clock speed [in Hz], must be <= 72MHz */
42 #define CLOCK_CORECLOCK (72000000U)
43 /* PLL configuration, set both values to zero to disable PLL usage. The values
44  * must be set to satisfy the following equation:
45  * CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
46  * with
47  * 1 <= CLOCK_PLL_DIV <= 2
48  * 2 <= CLOCK_PLL_MUL <= 17 */
49 #define CLOCK_PLL_DIV (1)
50 #define CLOCK_PLL_MUL (9)
51 /* AHB and APBx bus clock configuration, keep in mind the following constraints:
52  * ABP1 <= 36MHz
53  */
54 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
55 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
56 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
57 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
58 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
59 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
60 
66  #define DAC_NUMOF (0)
67 
73 #define ADC_NUMOF (0)
74 
80 static const timer_conf_t timer_config[] = {
81  {
82  .dev = TIM2,
83  .max = 0x0000ffff,
84  .rcc_mask = RCC_APB1ENR_TIM2EN,
85  .bus = APB1,
86  .irqn = TIM2_IRQn
87  },
88  {
89  .dev = TIM3,
90  .max = 0x0000ffff,
91  .rcc_mask = RCC_APB1ENR_TIM3EN,
92  .bus = APB1,
93  .irqn = TIM3_IRQn
94  }
95 };
96 
97 #define TIMER_0_ISR isr_tim2
98 #define TIMER_1_ISR isr_tim3
99 
100 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
101 
107 static const uart_conf_t uart_config[] = {
108  {
109  .dev = USART2,
110  .rcc_mask = RCC_APB1ENR_USART2EN,
111  .rx_pin = GPIO_PIN(PORT_A, 3),
112  .tx_pin = GPIO_PIN(PORT_A, 2),
113  .bus = APB1,
114  .irqn = USART2_IRQn
115  }
116 };
117 
118 #define UART_0_ISR (isr_usart2)
119 
120 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
121 
130 static const uint8_t spi_divtable[2][5] = {
131  { /* for APB1 @ 36000000Hz */
132  7, /* -> 140625Hz */
133  6, /* -> 281250Hz */
134  4, /* -> 1125000Hz */
135  2, /* -> 4500000Hz */
136  1 /* -> 9000000Hz */
137  },
138  { /* for APB2 @ 72000000Hz */
139  7, /* -> 281250Hz */
140  7, /* -> 281250Hz */
141  5, /* -> 1125000Hz */
142  3, /* -> 4500000Hz */
143  2 /* -> 9000000Hz */
144  }
145 };
146 
147 static const spi_conf_t spi_config[] = {
148  {
149  .dev = SPI1,
150  .mosi_pin = GPIO_PIN(PORT_B, 17),
151  .miso_pin = GPIO_PIN(PORT_B, 16),
152  .sclk_pin = GPIO_PIN(PORT_B, 15),
153  .cs_pin = GPIO_UNDEF,
154  .rccmask = RCC_APB2ENR_SPI1EN,
155  .apbbus = APB2
156  }
157 };
158 
159 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
160 
162 #ifdef __cplusplus
163 } /* end extern "C" */
164 #endif
165 
166 #endif /* PERIPH_CONF_H */
167 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.