boards/spark-core/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
32 /* high speed clock configuration:
33  * 0 := use internal HSI oscillator (always 8MHz)
34  * HSE frequency value := use external HSE oscillator with given freq [in Hz]
35  * must be 4000000 <= value <= 16000000 */
36 #define CLOCK_HSE (8000000U)
37 /* low speed clock configuration:
38  * 0 := use internal LSI oscillator (~40kHz)
39  * 1 := use extern LSE oscillator, always 32.768kHz */
40 #define CLOCK_LSE (0)
41 /* targeted system clock speed [in Hz], must be <= 72MHz */
42 #define CLOCK_CORECLOCK (72000000U)
43 /* PLL configuration, set both values to zero to disable PLL usage. The values
44  * must be set to satisfy the following equation:
45  * CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
46  * with
47  * 1 <= CLOCK_PLL_DIV <= 2
48  * 2 <= CLOCK_PLL_MUL <= 17 */
49 #define CLOCK_PLL_DIV (1)
50 #define CLOCK_PLL_MUL (9)
51 /* AHB and APBx bus clock configuration, keep in mind the following constraints:
52  * ABP1 <= 36MHz
53  */
54 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
55 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
56 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
57 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
58 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
59 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
60 
66 #define ADC_NUMOF (0)
67 
73 static const timer_conf_t timer_config[] = {
74  {
75  .dev = TIM2,
76  .max = 0x0000ffff,
77  .rcc_mask = RCC_APB1ENR_TIM2EN,
78  .bus = APB1,
79  .irqn = TIM2_IRQn
80  },
81  {
82  .dev = TIM3,
83  .max = 0x0000ffff,
84  .rcc_mask = RCC_APB1ENR_TIM3EN,
85  .bus = APB1,
86  .irqn = TIM3_IRQn
87  }
88 };
89 
90 #define TIMER_0_ISR isr_tim2
91 #define TIMER_1_ISR isr_tim3
92 
93 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
94 
100 static const uart_conf_t uart_config[] = {
101  {
102  .dev = USART2,
103  .rcc_mask = RCC_APB1ENR_USART2EN,
104  .rx_pin = GPIO_PIN(PORT_A, 3),
105  .tx_pin = GPIO_PIN(PORT_A, 2),
106  .bus = APB1,
107  .irqn = USART2_IRQn
108  }
109 };
110 
111 #define UART_0_ISR (isr_usart2)
112 
113 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
114 
123 static const uint8_t spi_divtable[2][5] = {
124  { /* for APB1 @ 36000000Hz */
125  7, /* -> 140625Hz */
126  6, /* -> 281250Hz */
127  4, /* -> 1125000Hz */
128  2, /* -> 4500000Hz */
129  1 /* -> 9000000Hz */
130  },
131  { /* for APB2 @ 72000000Hz */
132  7, /* -> 281250Hz */
133  7, /* -> 281250Hz */
134  5, /* -> 1125000Hz */
135  3, /* -> 4500000Hz */
136  2 /* -> 9000000Hz */
137  }
138 };
139 
140 static const spi_conf_t spi_config[] = {
141  {
142  .dev = SPI1,
143  .mosi_pin = GPIO_PIN(PORT_B, 17),
144  .miso_pin = GPIO_PIN(PORT_B, 16),
145  .sclk_pin = GPIO_PIN(PORT_B, 15),
146  .cs_pin = GPIO_UNDEF,
147  .rccmask = RCC_APB2ENR_SPI1EN,
148  .apbbus = APB2
149  }
150 };
151 
152 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
153 
155 #ifdef __cplusplus
156 } /* end extern "C" */
157 #endif
158 
159 #endif /* PERIPH_CONF_H */
160 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
NRF_TIMER_Type * dev
timer device
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
Timer configuration.
cc2538_ssi_t * dev
SSI device.