periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35  /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 72MHz */
37  #define CLOCK_CORECLOCK (72000000U)
38  /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40  #define CLOCK_HSE (8000000U)
41  /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43  #define CLOCK_LSE (0U)
44  /* peripheral clock setup */
45  #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46  #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47  #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
48  #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
49  #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
50  #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
51 
52  /* PLL factors */
53  #define CLOCK_PLL_PREDIV (1)
54  #define CLOCK_PLL_MUL (9)
55 
61 static const timer_conf_t timer_config[] = {
62  {
63  .dev = TIM2,
64  .max = 0x0000ffff,
65  .rcc_mask = RCC_APB1ENR_TIM2EN,
66  .bus = APB1,
67  .irqn = TIM2_IRQn
68  },
69  {
70  .dev = TIM3,
71  .max = 0x0000ffff,
72  .rcc_mask = RCC_APB1ENR_TIM3EN,
73  .bus = APB1,
74  .irqn = TIM3_IRQn
75  }
76 };
77 
78 #define TIMER_0_ISR isr_tim2
79 #define TIMER_1_ISR isr_tim3
80 
81 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
82 
88 static const uart_conf_t uart_config[] = {
89  {
90  .dev = USART2,
91  .rcc_mask = RCC_APB1ENR_USART2EN,
92  .rx_pin = GPIO_PIN(PORT_A, 3),
93  .tx_pin = GPIO_PIN(PORT_A, 2),
94  .bus = APB1,
95  .irqn = USART2_IRQn
96  }
97 };
98 
99 #define UART_0_ISR (isr_usart2)
100 
101 #define UART_NUMOF ARRAY_SIZE(uart_config)
102 
111 static const uint8_t spi_divtable[2][5] = {
112  { /* for APB1 @ 36000000Hz */
113  7, /* -> 140625Hz */
114  6, /* -> 281250Hz */
115  4, /* -> 1125000Hz */
116  2, /* -> 4500000Hz */
117  1 /* -> 9000000Hz */
118  },
119  { /* for APB2 @ 72000000Hz */
120  7, /* -> 281250Hz */
121  7, /* -> 281250Hz */
122  5, /* -> 1125000Hz */
123  3, /* -> 4500000Hz */
124  2 /* -> 9000000Hz */
125  }
126 };
127 
128 static const spi_conf_t spi_config[] = {
129  {
130  .dev = SPI1,
131  .mosi_pin = GPIO_PIN(PORT_B, 17),
132  .miso_pin = GPIO_PIN(PORT_B, 16),
133  .sclk_pin = GPIO_PIN(PORT_B, 15),
134  .cs_pin = GPIO_UNDEF,
135  .rccmask = RCC_APB2ENR_SPI1EN,
136  .apbbus = APB2
137  }
138 };
139 
140 #define SPI_NUMOF ARRAY_SIZE(spi_config)
141 
143 #ifdef __cplusplus
144 } /* end extern "C" */
145 #endif
146 
147 #endif /* PERIPH_CONF_H */
148 
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:435
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
NRF_TIMER_Type * dev
timer device
port A
Definition: periph_cpu.h:36
APB1 bus.
Definition: periph_cpu.h:147
UART device configuration.
Definition: periph_cpu.h:166
APB2 bus.
Definition: periph_cpu.h:148
static const uint8_t spi_divtable[2][5]
Shared SPI clock div table.
Definition: periph_conf.h:161
SPI configuration structure type.
Definition: periph_cpu.h:273
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
Timer configuration.
Definition: periph_cpu.h:288
port B
Definition: periph_cpu.h:37