boards/spark-core/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
32 #define CLOCK_HSE (8000000U) /* frequency of external oscillator */
33 #define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
34 /* configuration of PLL prescaler and multiply values */
35 /* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
36 #define CLOCK_PLL_DIV (1)
37 #define CLOCK_PLL_MUL (9)
38 /* configuration of peripheral bus clock prescalers */
39 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
40 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */
41 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* APB1 clock -> 36MHz */
42 /* resulting bus clocks */
43 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
44 #define CLOCK_APB2 (CLOCK_CORECLOCK)
45 
51  #define DAC_NUMOF (0)
52 
58 #define ADC_NUMOF (0)
59 
65 static const timer_conf_t timer_config[] = {
66  {
67  .dev = TIM2,
68  .max = 0x0000ffff,
69  .rcc_mask = RCC_APB1ENR_TIM2EN,
70  .bus = APB1,
71  .irqn = TIM2_IRQn
72  },
73  {
74  .dev = TIM3,
75  .max = 0x0000ffff,
76  .rcc_mask = RCC_APB1ENR_TIM3EN,
77  .bus = APB1,
78  .irqn = TIM3_IRQn
79  }
80 };
81 
82 #define TIMER_0_ISR isr_tim2
83 #define TIMER_1_ISR isr_tim3
84 
85 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
86 
92 static const uart_conf_t uart_config[] = {
93  {
94  .dev = USART2,
95  .rcc_mask = RCC_APB1ENR_USART2EN,
96  .rx_pin = GPIO_PIN(PORT_A, 3),
97  .tx_pin = GPIO_PIN(PORT_A, 2),
98  .bus = APB1,
99  .irqn = USART2_IRQn
100  }
101 };
102 
103 #define UART_0_ISR (isr_usart2)
104 
105 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
106 
115 static const uint8_t spi_divtable[2][5] = {
116  { /* for APB1 @ 36000000Hz */
117  7, /* -> 140625Hz */
118  6, /* -> 281250Hz */
119  4, /* -> 1125000Hz */
120  2, /* -> 4500000Hz */
121  1 /* -> 9000000Hz */
122  },
123  { /* for APB2 @ 72000000Hz */
124  7, /* -> 281250Hz */
125  7, /* -> 281250Hz */
126  5, /* -> 1125000Hz */
127  3, /* -> 4500000Hz */
128  2 /* -> 9000000Hz */
129  }
130 };
131 
132 static const spi_conf_t spi_config[] = {
133  {
134  .dev = SPI1,
135  .mosi_pin = GPIO_PIN(PORT_B, 17),
136  .miso_pin = GPIO_PIN(PORT_B, 16),
137  .sclk_pin = GPIO_PIN(PORT_B, 15),
138  .cs_pin = GPIO_UNDEF,
139  .rccmask = RCC_APB2ENR_SPI1EN,
140  .apbbus = APB2
141  }
142 };
143 
144 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
145 
147 #ifdef __cplusplus
148 } /* end extern "C" */
149 #endif
150 
151 #endif /* PERIPH_CONF_H */
152 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.