periph_conf.h
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1 /*
2  * Copyright (C) 2014 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser General
5  * Public License v2.1. See the file LICENSE in the top level directory for more
6  * details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* high speed clock configuration:
33  * 0 := use internal HSI oscillator (always 8MHz)
34  * HSE frequency value := use external HSE oscillator with given freq [in Hz]
35  * must be 4000000 <= value <= 16000000 */
36 #define CLOCK_HSE (8000000U)
37 /* low speed clock configuration:
38  * 0 := use internal LSI oscillator (~40kHz)
39  * 1 := use extern LSE oscillator, always 32.768kHz */
40 #define CLOCK_LSE (0)
41 /* targeted system clock speed [in Hz], must be <= 72MHz */
42 #define CLOCK_CORECLOCK (72000000U)
43 /* PLL configuration, set both values to zero to disable PLL usage. The values
44  * must be set to satisfy the following equation:
45  * CORECLOCK := CLOCK_SOURCE / PLL_DIV * PLL_MUL
46  * with
47  * 1 <= CLOCK_PLL_DIV <= 2
48  * 2 <= CLOCK_PLL_MUL <= 17 */
49 #define CLOCK_PLL_DIV (1)
50 #define CLOCK_PLL_MUL (9)
51 /* AHB and APBx bus clock configuration, keep in mind the following constraints:
52  * ABP1 <= 36MHz
53  */
54 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
55 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
56 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
57 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
58 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
59 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
60 
66 static const timer_conf_t timer_config[] = {
67  {
68  .dev = TIM2,
69  .max = 0x0000ffff,
70  .rcc_mask = RCC_APB1ENR_TIM2EN,
71  .bus = APB1,
72  .irqn = TIM2_IRQn
73  },
74  {
75  .dev = TIM3,
76  .max = 0x0000ffff,
77  .rcc_mask = RCC_APB1ENR_TIM3EN,
78  .bus = APB1,
79  .irqn = TIM3_IRQn
80  }
81 };
82 
83 #define TIMER_0_ISR isr_tim2
84 #define TIMER_1_ISR isr_tim3
85 
86 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
87 
93 static const uart_conf_t uart_config[] = {
94  {
95  .dev = USART2,
96  .rcc_mask = RCC_APB1ENR_USART2EN,
97  .rx_pin = GPIO_PIN(PORT_A, 3),
98  .tx_pin = GPIO_PIN(PORT_A, 2),
99  .bus = APB1,
100  .irqn = USART2_IRQn
101  }
102 };
103 
104 #define UART_0_ISR (isr_usart2)
105 
106 #define UART_NUMOF ARRAY_SIZE(uart_config)
107 
116 static const uint8_t spi_divtable[2][5] = {
117  { /* for APB1 @ 36000000Hz */
118  7, /* -> 140625Hz */
119  6, /* -> 281250Hz */
120  4, /* -> 1125000Hz */
121  2, /* -> 4500000Hz */
122  1 /* -> 9000000Hz */
123  },
124  { /* for APB2 @ 72000000Hz */
125  7, /* -> 281250Hz */
126  7, /* -> 281250Hz */
127  5, /* -> 1125000Hz */
128  3, /* -> 4500000Hz */
129  2 /* -> 9000000Hz */
130  }
131 };
132 
133 static const spi_conf_t spi_config[] = {
134  {
135  .dev = SPI1,
136  .mosi_pin = GPIO_PIN(PORT_B, 17),
137  .miso_pin = GPIO_PIN(PORT_B, 16),
138  .sclk_pin = GPIO_PIN(PORT_B, 15),
139  .cs_pin = GPIO_UNDEF,
140  .rccmask = RCC_APB2ENR_SPI1EN,
141  .apbbus = APB2
142  }
143 };
144 
145 #define SPI_NUMOF ARRAY_SIZE(spi_config)
146 
148 #ifdef __cplusplus
149 } /* end extern "C" */
150 #endif
151 
152 #endif /* PERIPH_CONF_H */
153 
static const spi_conf_t spi_config[]
Static array with configuration for declared I2C devices.
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
APB1 bus.
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:435
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
NRF_TIMER_Type * dev
timer device
port A
Definition: periph_cpu.h:36
static const uart_conf_t uart_config[]
Static array with configuration for declared I2C devices.
APB2 bus.
UART device configuration.
Definition: periph_cpu.h:166
static const uint8_t spi_divtable[2][5]
Shared SPI clock div table.
Definition: periph_conf.h:166
SPI configuration structure type.
Definition: periph_cpu.h:271
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
Timer configuration.
Definition: periph_cpu.h:286
port B
Definition: periph_cpu.h:37