periph_conf.h
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1 /*
2  * Copyright (C) 2017 Kees Bakker, SODAQ
3  * 2018 HAW Hamburg
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include <stdint.h>
25 
26 #include "cpu.h"
27 #include "periph_cpu.h"
28 #include "cfg_clock_default.h"
29 #include "cfg_rtc_default.h"
30 #include "cfg_rtt_default.h"
31 #include "cfg_spi_default.h"
32 #include "cfg_timer_default.h"
33 #include "cfg_usbdev_default.h"
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
44 static const uart_conf_t uart_config[] = {
45  {
46  .dev = &SERCOM5->USART,
47  .rx_pin = GPIO_PIN(PB, 30), /* D0, RX Pin */
48  .tx_pin = GPIO_PIN(PB, 31), /* D1, TX Pin */
49  .mux = GPIO_MUX_D,
50  .rx_pad = UART_PAD_RX_1,
51  .tx_pad = UART_PAD_TX_0,
52  .flags = UART_FLAG_NONE,
53  .gclk_src = GCLK_CLKCTRL_GEN_GCLK0
54  },
55  {
56  .dev = &SERCOM0->USART,
57  .rx_pin = GPIO_PIN(PA,5),
58  .tx_pin = GPIO_PIN(PA,6),
59  .mux = GPIO_MUX_D,
60  .rx_pad = UART_PAD_RX_1,
61  .tx_pad = UART_PAD_TX_2,
62  .flags = UART_FLAG_NONE,
63  .gclk_src = GCLK_CLKCTRL_GEN_GCLK0
64  },
65 };
66 
67 /* interrupt function name mapping */
68 #define UART_0_ISR isr_sercom5
69 #define UART_1_ISR isr_sercom0
70 
71 #define UART_NUMOF ARRAY_SIZE(uart_config)
72 
79 /* ADC Default values */
80 #define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512
81 
82 #define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
83 #define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_DIV2
84 #define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INTVCC1
85 
86 static const adc_conf_chan_t adc_channels[] = {
87  /* port, pin, muxpos */
88  {GPIO_PIN(PB, 0), ADC_INPUTCTRL_MUXPOS_PIN8}, /* A0 */
89  {GPIO_PIN(PB, 1), ADC_INPUTCTRL_MUXPOS_PIN9}, /* A1 */
90  {GPIO_PIN(PB, 2), ADC_INPUTCTRL_MUXPOS_PIN10}, /* A2 */
91  {GPIO_PIN(PB, 3), ADC_INPUTCTRL_MUXPOS_PIN11}, /* A3 */
92  {GPIO_PIN(PA, 8), ADC_INPUTCTRL_MUXPOS_PIN16}, /* A4 */
93  {GPIO_PIN(PA, 9), ADC_INPUTCTRL_MUXPOS_PIN17}, /* A5 */
94  {GPIO_PIN(PA, 10), ADC_INPUTCTRL_MUXPOS_PIN18}, /* GROVE1/A6 */
95  {GPIO_PIN(PA, 11), ADC_INPUTCTRL_MUXPOS_PIN19}, /* GROVE2/A7 */
96  {GPIO_PIN(PB, 5), ADC_INPUTCTRL_MUXPOS_PIN13}, /* BAT_VOLT/A8 */
97  {GPIO_PIN(PA, 2), ADC_INPUTCTRL_MUXPOS_PIN0}, /* D2/DAC */
98  {GPIO_PIN(PA, 3), ADC_INPUTCTRL_MUXPOS_PIN1}, /* AREF */
99 };
100 
101 #define ADC_NUMOF ARRAY_SIZE(adc_channels)
102 
108 static const i2c_conf_t i2c_config[] = {
109  {
110  .dev = &(SERCOM1->I2CM),
111  .speed = I2C_SPEED_NORMAL,
112  .scl_pin = GPIO_PIN(PA, 17),
113  .sda_pin = GPIO_PIN(PA, 16),
114  .mux = GPIO_MUX_C,
115  .gclk_src = GCLK_CLKCTRL_GEN_GCLK0,
116  .flags = I2C_FLAG_NONE
117  }
118 };
119 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
120 
122 #ifdef __cplusplus
123 }
124 #endif
125 
126 #endif /* PERIPH_CONF_H */
127 
select peripheral function D
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
I2C configuration options.
Definition: periph_cpu.h:128
Default clock configuration for SODAQ boards.
No flags set.
static const gpio_t adc_channels[]
Static array with declared ADC channels.
port A
Definition: periph_cpu.h:87
port B
Definition: periph_cpu.h:88
Default usbdev configuration for SODAQ boards.
select pad 1
select pad 0
No flags set.
ADC Channel Configuration.
select peripheral function C
Default RTC configuration for SODAQ boards.
static const i2c_conf_t i2c_config[]
Static array with configuration for declared I2C devices.
select pad 2
static const uart_conf_t uart_config[]
Static array with configuration for declared I2C devices.
UART device configuration.
Definition: periph_cpu.h:166
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:240
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
normal mode: ~100 kbit/s
Definition: i2c.h:183