boards/sodaq-autonomo/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Kees Bakker, SODAQ
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include <stdint.h>
23 
24 #include "cpu.h"
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
62 #define CLOCK_USE_PLL (1)
63 
64 #if CLOCK_USE_PLL
65 /* edit these values to adjust the PLL output frequency */
66 #define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
67 #define CLOCK_PLL_DIV (1U) /* adjust to your needs */
68 /* generate the actual used core clock frequency */
69 #define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
70 #else
71 /* edit this value to your needs */
72 #define CLOCK_DIV (1U)
73 /* generate the actual core clock frequency */
74 #define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
75 #endif
76 
82 #define TIMER_NUMOF (2U)
83 #define TIMER_0_EN 1
84 #define TIMER_1_EN 1
85 
86 /* Timer 0 configuration */
87 #define TIMER_0_DEV TC3->COUNT16
88 #define TIMER_0_CHANNELS 2
89 #define TIMER_0_MAX_VALUE (0xffff)
90 #define TIMER_0_ISR isr_tc3
91 
92 /* Timer 1 configuration */
93 #define TIMER_1_DEV TC4->COUNT32
94 #define TIMER_1_CHANNELS 2
95 #define TIMER_1_MAX_VALUE (0xffffffff)
96 #define TIMER_1_ISR isr_tc4
97 
104 static const uart_conf_t uart_config[] = {
105  {
106  .dev = &SERCOM0->USART,
107  .rx_pin = GPIO_PIN(PA,9),
108  .tx_pin = GPIO_PIN(PA,10),
109  .mux = GPIO_MUX_C,
110  .rx_pad = UART_PAD_RX_1,
111  .tx_pad = UART_PAD_TX_2,
112  },
113  {
114  .dev = &SERCOM5->USART,
115  .rx_pin = GPIO_PIN(PB,31),
116  .tx_pin = GPIO_PIN(PB,30),
117  .mux = GPIO_MUX_D,
118  .rx_pad = UART_PAD_RX_1,
119  .tx_pad = UART_PAD_TX_0_RTS_2_CTS_3,
120  },
121  {
122  .dev = &SERCOM4->USART,
123  .rx_pin = GPIO_PIN(PB,13),
124  .tx_pin = GPIO_PIN(PA,14),
125  .mux = GPIO_MUX_C,
126  .rx_pad = UART_PAD_RX_1,
127  .tx_pad = UART_PAD_TX_2,
128  },
129  {
130  .dev = &SERCOM1->USART,
131  .rx_pin = GPIO_PIN(PA,17),
132  .tx_pin = GPIO_PIN(PA,18),
133  .mux = GPIO_MUX_C,
134  .rx_pad = UART_PAD_RX_1,
135  .tx_pad = UART_PAD_TX_2,
136  }
137 };
138 
139 /* interrupt function name mapping */
140 #define UART_0_ISR isr_sercom0
141 #define UART_1_ISR isr_sercom5
142 #define UART_2_ISR isr_sercom4
143 #define UART_3_ISR isr_sercom1
144 
145 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
146 
152 #define PWM_0_EN 1
153 #define PWM_1_EN 1
154 #define PWM_MAX_CHANNELS 3
155 /* for compatibility with test application */
156 #define PWM_0_CHANNELS PWM_MAX_CHANNELS
157 #define PWM_1_CHANNELS PWM_MAX_CHANNELS
158 
159 /* PWM device configuration */
160 static const pwm_conf_t pwm_config[] = {
161 #if PWM_0_EN
162  {TCC1, {
163  /* GPIO pin, MUX value, TCC channel */
164  { GPIO_PIN(PA, 6), GPIO_MUX_E, 0 },
165  { GPIO_PIN(PA, 7), GPIO_MUX_E, 1 },
166  { GPIO_UNDEF, (gpio_mux_t)0, 2 }
167  }},
168 #endif
169 #if PWM_1_EN
170  {TCC0, {
171  /* GPIO pin, MUX value, TCC channel */
172  { GPIO_PIN(PA, 16), GPIO_MUX_F, 0 },
173  { GPIO_PIN(PA, 18), GPIO_MUX_F, 2 },
174  { GPIO_PIN(PA, 19), GPIO_MUX_F, 3 }
175  }}
176 #endif
177 };
178 
179 /* number of devices that are actually defined */
180 #define PWM_NUMOF (2U)
181 
187 static const spi_conf_t spi_config[] = {
188  {
189  .dev = &SERCOM3->SPI,
190  .miso_pin = GPIO_PIN(PA, 22),
191  .mosi_pin = GPIO_PIN(PA, 20),
192  .clk_pin = GPIO_PIN(PA, 21),
193  .miso_mux = GPIO_MUX_C,
194  .mosi_mux = GPIO_MUX_D,
195  .clk_mux = GPIO_MUX_D,
196  .miso_pad = SPI_PAD_MISO_0,
197  .mosi_pad = SPI_PAD_MOSI_2_SCK_3,
198  },
199 };
200 
201 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
202 
208 #define I2C_NUMOF (1U)
209 #define I2C_0_EN 1
210 #define I2C_1_EN 0
211 #define I2C_2_EN 0
212 #define I2C_3_EN 0
213 #define I2C_IRQ_PRIO 1
214 
215 #define I2C_0_DEV SERCOM2->I2CM
216 #define I2C_0_IRQ SERCOM2_IRQn
217 #define I2C_0_ISR isr_sercom2
218 /* I2C 0 GCLK */
219 #define I2C_0_GCLK_ID SERCOM2_GCLK_ID_CORE
220 #define I2C_0_GCLK_ID_SLOW SERCOM2_GCLK_ID_SLOW
221 /* I2C 0 pin configuration */
222 #define I2C_0_SDA GPIO_PIN(PA, 12)
223 #define I2C_0_SCL GPIO_PIN(PA, 13)
224 #define I2C_0_MUX GPIO_MUX_C
225 
230 #define RTC_NUMOF (1U)
231 #define RTC_DEV RTC->MODE2
232 
238 #define RTT_NUMOF (1U)
239 #define RTT_DEV RTC->MODE0
240 #define RTT_IRQ RTC_IRQn
241 #define RTT_IRQ_PRIO 10
242 #define RTT_ISR isr_rtc
243 #define RTT_MAX_VALUE (0xffffffff)
244 #define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
245 #define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
246 
248 #ifdef __cplusplus
249 }
250 #endif
251 
252 #endif /* PERIPH_CONF_H */
253 
select peripheral function D
USART_TypeDef * dev
USART device used.
select peripheral function E
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
select peripheral function F
PWM configuration structure.
select peripheral function C
gpio_mux_t
Available MUX values for configuring a pin's alternate function.
UART device configuration.
use pad 2 for MOSI, pad 3 for SCK
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
cc2538_ssi_t * dev
SSI device.