periph_conf.h
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1 /*
2  * Copyright (C) 2018 HAW Hamburg
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include <stdint.h>
24 
25 #include "cpu.h"
26 #include "periph_cpu.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
63 #define CLOCK_USE_PLL (1)
64 
65 #if CLOCK_USE_PLL
66 /* edit these values to adjust the PLL output frequency */
67 #define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
68 #define CLOCK_PLL_DIV (1U) /* adjust to your needs */
69 #define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
70 #else
71 /* edit this value to your needs */
72 #define CLOCK_DIV (1U)
73 /* generate the actual core clock frequency */
74 #define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
75 #endif
76 
82 static const tc32_conf_t timer_config[] = {
83  { /* Timer 0 - System Clock */
84  .dev = TC3,
85  .irq = TC3_IRQn,
86  .pm_mask = PM_APBCMASK_TC3,
87  .gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
88 #if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
89  .gclk_src = GCLK_CLKCTRL_GEN(1),
90  .prescaler = TC_CTRLA_PRESCALER_DIV1,
91 #else
92  .gclk_src = GCLK_CLKCTRL_GEN(0),
93  .prescaler = TC_CTRLA_PRESCALER_DIV8,
94 #endif
95  .flags = TC_CTRLA_MODE_COUNT16,
96  },
97  { /* Timer 1 */
98  .dev = TC4,
99  .irq = TC4_IRQn,
100  .pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
101  .gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
102 #if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
103  .gclk_src = GCLK_CLKCTRL_GEN(1),
104  .prescaler = TC_CTRLA_PRESCALER_DIV1,
105 #else
106  .gclk_src = GCLK_CLKCTRL_GEN(0),
107  .prescaler = TC_CTRLA_PRESCALER_DIV8,
108 #endif
109  .flags = TC_CTRLA_MODE_COUNT32,
110  }
111 };
112 
113 #define TIMER_0_MAX_VALUE 0xffff
114 
115 /* interrupt function name mapping */
116 #define TIMER_0_ISR isr_tc3
117 #define TIMER_1_ISR isr_tc4
118 
119 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
120 
126 static const uart_conf_t uart_config[] = {
127  {
128  .dev = &SERCOM3->USART,
129  .rx_pin = GPIO_PIN(PA, 23),
130  .tx_pin = GPIO_PIN(PA, 22),
131  .mux = GPIO_MUX_C,
132  .rx_pad = UART_PAD_RX_1,
133  .tx_pad = UART_PAD_TX_0,
134  .flags = UART_FLAG_NONE,
135  .gclk_src = GCLK_CLKCTRL_GEN_GCLK0,
136  },
137  {
138  .dev = &SERCOM4->USART,
139  .rx_pin = GPIO_PIN(PB, 9),
140  .tx_pin = GPIO_PIN(PB, 8),
141  .mux = GPIO_MUX_D,
142  .rx_pad = UART_PAD_RX_1,
143  .tx_pad = UART_PAD_TX_0,
144  .flags = UART_FLAG_NONE,
145  .gclk_src = GCLK_CLKCTRL_GEN_GCLK0,
146  }
147 };
148 
149 /* interrupt function name mapping */
150 #define UART_0_ISR isr_sercom3
151 #define UART_1_ISR isr_sercom4
152 
153 #define UART_NUMOF ARRAY_SIZE(uart_config)
154 
160 static const spi_conf_t spi_config[] = {
161  {
162  .dev = &SERCOM1->SPI,
163  .miso_pin = GPIO_PIN(PA, 19),
164  .mosi_pin = GPIO_PIN(PA, 16),
165  .clk_pin = GPIO_PIN(PA, 17),
166  .miso_mux = GPIO_MUX_C,
167  .mosi_mux = GPIO_MUX_C,
168  .clk_mux = GPIO_MUX_C,
169  .miso_pad = SPI_PAD_MISO_3,
170  .mosi_pad = SPI_PAD_MOSI_0_SCK_1
171  }
172 };
173 
174 #define SPI_NUMOF ARRAY_SIZE(spi_config)
175 
180 static const i2c_conf_t i2c_config[] = {
181  {
182  .dev = &(SERCOM0->I2CM),
183  .speed = I2C_SPEED_NORMAL,
184  .scl_pin = GPIO_PIN(PA, 8),
185  .sda_pin = GPIO_PIN(PA, 9),
186  .mux = GPIO_MUX_C,
187  .gclk_src = GCLK_CLKCTRL_GEN_GCLK0,
188  .flags = I2C_FLAG_NONE
189  },
190  {
191  .dev = &(SERCOM2->I2CM),
192  .speed = I2C_SPEED_NORMAL,
193  .scl_pin = GPIO_PIN(PA, 12),
194  .sda_pin = GPIO_PIN(PA, 13),
195  .mux = GPIO_MUX_C,
196  .gclk_src = GCLK_CLKCTRL_GEN_GCLK0,
197  .flags = I2C_FLAG_NONE
198  }
199 };
200 
201 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
202 
207 #define RTC_DEV RTC->MODE2
208 
216 /* ADC Default values */
217 #define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512
218 
219 #define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
220 #define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
221 #define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
222 
223 /* Digital pins (1 to 6) on the board can be configured as analog inputs */
224 static const adc_conf_chan_t adc_channels[] = {
225  /* port, pin, muxpos */
226  { GPIO_PIN(PA, 4), ADC_INPUTCTRL_MUXPOS_PIN4 }, /* Digital 1 */
227  { GPIO_PIN(PA, 5), ADC_INPUTCTRL_MUXPOS_PIN5 }, /* Digital 2 */
228  { GPIO_PIN(PA, 6), ADC_INPUTCTRL_MUXPOS_PIN6 }, /* Digital 3 */
229  { GPIO_PIN(PA, 7), ADC_INPUTCTRL_MUXPOS_PIN7 }, /* Digital 4 */
230  { GPIO_PIN(PA, 3), ADC_INPUTCTRL_MUXPOS_PIN1 }, /* Digital 5 */
231  { GPIO_PIN(PA, 2), ADC_INPUTCTRL_MUXPOS_PIN0 }, /* Digital 6 */
232 };
233 
234 #define ADC_NUMOF ARRAY_SIZE(adc_channels)
235 
241 static const sam0_common_usb_config_t sam_usbdev_config[] = {
242  {
243  .dm = GPIO_PIN(PA, 24),
244  .dp = GPIO_PIN(PA, 25),
245  .d_mux = GPIO_MUX_G,
246  .device = &USB->DEVICE,
247  }
248 };
251 #ifdef __cplusplus
252 }
253 #endif
254 
255 #endif /* PERIPH_CONF_H */
256 
select peripheral function D
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
I2C configuration options.
Definition: periph_cpu.h:128
Tc * dev
pointer to the used Timer device
No flags set.
static const gpio_t adc_channels[]
Static array with declared ADC channels.
port A
Definition: periph_cpu.h:87
port B
Definition: periph_cpu.h:88
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:435
select pad 1
select pad 0
gpio_t dm
D- line gpio.
No flags set.
ADC Channel Configuration.
select peripheral function C
select peripheral function G
USB peripheral parameters.
use pad 0 for MISO line
UART device configuration.
Definition: periph_cpu.h:166
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:240
SPI configuration structure type.
Definition: periph_cpu.h:271
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
normal mode: ~100 kbit/s
Definition: i2c.h:183
use pad 0 for MOSI, pad 1 for SCK
Timer device configuration.