boards/samr21-xpro/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014-2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include <stdint.h>
26 
27 #include "cpu.h"
28 #include "periph_cpu.h"
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
66 #define CLOCK_USE_PLL (1)
67 
68 #if CLOCK_USE_PLL
69 /* edit these values to adjust the PLL output frequency */
70 #define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
71 #define CLOCK_PLL_DIV (1U) /* adjust to your needs */
72 /* generate the actual used core clock frequency */
73 #define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
74 #elif CLOCK_USE_XOSC32_DFLL
75  /* Settings for 32 kHz external oscillator and 48 MHz DFLL */
76 #define CLOCK_CORECLOCK (48000000U)
77 #define CLOCK_XOSC32K (32768UL)
78 #define CLOCK_8MHZ (1)
79 #define GEN2_ULP32K (1)
80 #else
81 /* edit this value to your needs */
82 #define CLOCK_DIV (1U)
83 /* generate the actual core clock frequency */
84 #define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
85 #endif
86 
92 #define TIMER_NUMOF (2U)
93 #define TIMER_0_EN 1
94 #define TIMER_1_EN 1
95 
96 /* Timer 0 configuration */
97 #define TIMER_0_DEV TC3->COUNT16
98 #define TIMER_0_CHANNELS 2
99 #define TIMER_0_MAX_VALUE (0xffff)
100 #define TIMER_0_ISR isr_tc3
101 
102 /* Timer 1 configuration */
103 #define TIMER_1_DEV TC4->COUNT32
104 #define TIMER_1_CHANNELS 2
105 #define TIMER_1_MAX_VALUE (0xffffffff)
106 #define TIMER_1_ISR isr_tc4
107 
113 static const uart_conf_t uart_config[] = {
114  {
115  .dev = &SERCOM0->USART,
116  .rx_pin = GPIO_PIN(PA,5),
117  .tx_pin = GPIO_PIN(PA,4),
118  .mux = GPIO_MUX_D,
119  .rx_pad = UART_PAD_RX_1,
120  .tx_pad = UART_PAD_TX_0
121  },
122  {
123  .dev = &SERCOM5->USART,
124  .rx_pin = GPIO_PIN(PA,23),
125  .tx_pin = GPIO_PIN(PA,22),
126  .mux = GPIO_MUX_D,
127  .rx_pad = UART_PAD_RX_1,
128  .tx_pad = UART_PAD_TX_0
129  }
130 };
131 
132 /* interrupt function name mapping */
133 #define UART_0_ISR isr_sercom0
134 #define UART_1_ISR isr_sercom5
135 
136 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
137 
143 #define PWM_0_EN 1
144 #define PWM_1_EN 1
145 #define PWM_MAX_CHANNELS 3
146 /* for compatibility with test application */
147 #define PWM_0_CHANNELS PWM_MAX_CHANNELS
148 #define PWM_1_CHANNELS PWM_MAX_CHANNELS
149 
150 /* PWM device configuration */
151 static const pwm_conf_t pwm_config[] = {
152 #if PWM_0_EN
153  {TCC1, {
154  /* GPIO pin, MUX value, TCC channel */
155  { GPIO_PIN(PA, 6), GPIO_MUX_E, 0 },
156  { GPIO_PIN(PA, 7), GPIO_MUX_E, 1 },
157  { GPIO_UNDEF, (gpio_mux_t)0, 2 }
158  }},
159 #endif
160 #if PWM_1_EN
161  {TCC0, {
162  /* GPIO pin, MUX value, TCC channel */
163  { GPIO_PIN(PA, 16), GPIO_MUX_F, 0 },
164  { GPIO_PIN(PA, 18), GPIO_MUX_F, 2 },
165  { GPIO_PIN(PA, 19), GPIO_MUX_F, 3 }
166  }}
167 #endif
168 };
169 
170 /* number of devices that are actually defined */
171 #define PWM_NUMOF (2U)
172 
178 static const spi_conf_t spi_config[] = {
179  {
180  .dev = &SERCOM4->SPI,
181  .miso_pin = GPIO_PIN(PC, 19),
182  .mosi_pin = GPIO_PIN(PB, 30),
183  .clk_pin = GPIO_PIN(PC, 18),
184  .miso_mux = GPIO_MUX_F,
185  .mosi_mux = GPIO_MUX_F,
186  .clk_mux = GPIO_MUX_F,
187  .miso_pad = SPI_PAD_MISO_0,
188  .mosi_pad = SPI_PAD_MOSI_2_SCK_3
189  },
190  {
191  .dev = &SERCOM5->SPI,
192  .miso_pin = GPIO_PIN(PB, 2),
193  .mosi_pin = GPIO_PIN(PB, 22),
194  .clk_pin = GPIO_PIN(PB, 23),
195  .miso_mux = GPIO_MUX_D,
196  .mosi_mux = GPIO_MUX_D,
197  .clk_mux = GPIO_MUX_D,
198  .miso_pad = SPI_PAD_MISO_0,
199  .mosi_pad = SPI_PAD_MOSI_2_SCK_3
200  }
201 };
202 
203 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
204 
210 #define I2C_NUMOF (1U)
211 #define I2C_0_EN 1
212 #define I2C_1_EN 0
213 #define I2C_2_EN 0
214 #define I2C_3_EN 0
215 #define I2C_IRQ_PRIO 1
216 
217 #define I2C_0_DEV SERCOM3->I2CM
218 #define I2C_0_IRQ SERCOM3_IRQn
219 #define I2C_0_ISR isr_sercom3
220 /* I2C 0 GCLK */
221 #define I2C_0_GCLK_ID SERCOM3_GCLK_ID_CORE
222 #define I2C_0_GCLK_ID_SLOW SERCOM3_GCLK_ID_SLOW
223 /* I2C 0 pin configuration */
224 #define I2C_0_SDA GPIO_PIN(PA, 16)
225 #define I2C_0_SCL GPIO_PIN(PA, 17)
226 #define I2C_0_MUX GPIO_MUX_D
227 
232 #define RTC_NUMOF (1U)
233 #define RTC_DEV RTC->MODE2
234 
240 #define RTT_NUMOF (1U)
241 #define RTT_DEV RTC->MODE0
242 #define RTT_IRQ RTC_IRQn
243 #define RTT_IRQ_PRIO 10
244 #define RTT_ISR isr_rtc
245 #define RTT_MAX_VALUE (0xffffffff)
246 #define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
247 #define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
248 
254 #define ADC_0_EN 1
255 #define ADC_MAX_CHANNELS 14
256 /* ADC 0 device configuration */
257 #define ADC_0_DEV ADC
258 #define ADC_0_IRQ ADC_IRQn
259 
260 /* ADC 0 Default values */
261 #define ADC_0_CLK_SOURCE 0 /* GCLK_GENERATOR_0 */
262 #define ADC_0_PRESCALER ADC_CTRLB_PRESCALER_DIV512
263 
264 #define ADC_0_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
265 #define ADC_0_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
266 #define ADC_0_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
267 
268 static const adc_conf_chan_t adc_channels[] = {
269  /* port, pin, muxpos */
270  {GPIO_PIN(PA, 6), ADC_INPUTCTRL_MUXPOS_PIN6}, /* EXT1, pin 3 */
271  {GPIO_PIN(PA, 7), ADC_INPUTCTRL_MUXPOS_PIN7}, /* EXT1, pin 4 */
272 };
273 
274 #define ADC_0_CHANNELS (2U)
275 #define ADC_NUMOF ADC_0_CHANNELS
276 
277 #ifdef __cplusplus
278 }
279 #endif
280 
281 #endif /* PERIPH_CONF_H */
282 
select peripheral function D
USART_TypeDef * dev
USART device used.
select peripheral function E
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
select peripheral function F
ADC Channel Configuration.
PWM configuration structure.
gpio_mux_t
Available MUX values for configuring a pin&#39;s alternate function.
UART device configuration.
use pad 2 for MOSI, pad 3 for SCK
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
cc2538_ssi_t * dev
SSI device.