periph_conf.h
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1 /*
2  * Copyright (C) 2014-2015 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include <stdint.h>
26 
27 #include "cpu.h"
28 #include "periph_cpu.h"
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
66 #define CLOCK_USE_PLL (1)
67 #define CLOCK_USE_XOSC32_DFLL (0)
68 /*
69  * 0: use XOSC32K (always 32.768kHz) to clock GCLK2
70  * 1: use OSCULP32K factory calibrated (~32.768kHz) to clock GCLK2
71  *
72  * OSCULP32K is factory calibrated to be around 32.768kHz but this values can
73  * be of by a couple off % points, so prefer XOSC32K as default configuration.
74  */
75 #define GEN2_ULP32K (0)
76 
77 #if CLOCK_USE_PLL
78 /* edit these values to adjust the PLL output frequency */
79 #define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
80 #define CLOCK_PLL_DIV (1U) /* adjust to your needs */
81 /* generate the actual used core clock frequency */
82 #define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
83 #elif CLOCK_USE_XOSC32_DFLL
84  /* Settings for 32 kHz external oscillator and 48 MHz DFLL */
85 #define CLOCK_CORECLOCK (48000000U)
86 #define CLOCK_XOSC32K (32768UL)
87 #define CLOCK_8MHZ (1)
88 #else
89 /* edit this value to your needs */
90 #define CLOCK_DIV (1U)
91 /* generate the actual core clock frequency */
92 #define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
93 #endif
94 
100 static const tc32_conf_t timer_config[] = {
101  { /* Timer 0 - System Clock */
102  .dev = TC3,
103  .irq = TC3_IRQn,
104  .pm_mask = PM_APBCMASK_TC3,
105  .gclk_ctrl = GCLK_CLKCTRL_ID_TCC2_TC3,
106 #if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
107  .gclk_src = SAM0_GCLK_1MHZ,
108 #else
109  .gclk_src = SAM0_GCLK_MAIN,
110 #endif
111  .flags = TC_CTRLA_MODE_COUNT16,
112  },
113  { /* Timer 1 */
114  .dev = TC4,
115  .irq = TC4_IRQn,
116  .pm_mask = PM_APBCMASK_TC4 | PM_APBCMASK_TC5,
117  .gclk_ctrl = GCLK_CLKCTRL_ID_TC4_TC5,
118 #if CLOCK_USE_PLL || CLOCK_USE_XOSC32_DFLL
119  .gclk_src = SAM0_GCLK_1MHZ,
120 #else
121  .gclk_src = SAM0_GCLK_MAIN,
122 #endif
123  .flags = TC_CTRLA_MODE_COUNT32,
124  }
125 };
126 
127 #define TIMER_0_MAX_VALUE 0xffff
128 
129 /* interrupt function name mapping */
130 #define TIMER_0_ISR isr_tc3
131 #define TIMER_1_ISR isr_tc4
132 
133 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
134 
140 static const uart_conf_t uart_config[] = {
141  {
142  .dev = &SERCOM0->USART,
143  .rx_pin = GPIO_PIN(PA,5),
144  .tx_pin = GPIO_PIN(PA,4),
145 #ifdef MODULE_PERIPH_UART_HW_FC
146  .rts_pin = GPIO_PIN(PA,6),
147  .cts_pin = GPIO_PIN(PA,7),
148 #endif
149  .mux = GPIO_MUX_D,
150  .rx_pad = UART_PAD_RX_1,
151 #ifdef MODULE_PERIPH_UART_HW_FC
152  .tx_pad = UART_PAD_TX_0_RTS_2_CTS_3,
153 #else
154  .tx_pad = UART_PAD_TX_0,
155 #endif
156  .flags = UART_FLAG_NONE,
157  .gclk_src = SAM0_GCLK_MAIN,
158  },
159  {
160  .dev = &SERCOM5->USART,
161  .rx_pin = GPIO_PIN(PA,23),
162  .tx_pin = GPIO_PIN(PA,22),
163 #ifdef MODULE_PERIPH_UART_HW_FC
164  .rts_pin = GPIO_PIN(PB,22),
165  .cts_pin = GPIO_PIN(PB,23),
166 #endif
167  .mux = GPIO_MUX_D,
168  .rx_pad = UART_PAD_RX_1,
169 #ifdef MODULE_PERIPH_UART_HW_FC
170  .tx_pad = UART_PAD_TX_0_RTS_2_CTS_3,
171 #else
172  .tx_pad = UART_PAD_TX_0,
173 #endif
174  .flags = UART_FLAG_NONE,
175  .gclk_src = SAM0_GCLK_MAIN,
176  }
177 };
178 
179 /* interrupt function name mapping */
180 #define UART_0_ISR isr_sercom0
181 #define UART_1_ISR isr_sercom5
182 
183 #define UART_NUMOF ARRAY_SIZE(uart_config)
184 
190 #define PWM_0_EN 1
191 #define PWM_1_EN 1
192 
193 #if PWM_0_EN
194 /* PWM0 channels */
195 static const pwm_conf_chan_t pwm_chan0_config[] = {
196  /* GPIO pin, MUX value, TCC channel */
197  { GPIO_PIN(PA, 6), GPIO_MUX_E, 0 },
198  { GPIO_PIN(PA, 7), GPIO_MUX_E, 1 },
199 };
200 #endif
201 #if PWM_1_EN
202 /* PWM1 channels */
203 static const pwm_conf_chan_t pwm_chan1_config[] = {
204  /* GPIO pin, MUX value, TCC channel */
205  { GPIO_PIN(PA, 16), GPIO_MUX_F, 0 },
206  { GPIO_PIN(PA, 18), GPIO_MUX_F, 2 },
207  { GPIO_PIN(PA, 19), GPIO_MUX_F, 3 },
208 };
209 #endif
210 
211 /* PWM device configuration */
212 static const pwm_conf_t pwm_config[] = {
213 #if PWM_0_EN
214  {TCC_CONFIG(TCC1), pwm_chan0_config, ARRAY_SIZE(pwm_chan0_config), SAM0_GCLK_MAIN},
215 #endif
216 #if PWM_1_EN
217  {TCC_CONFIG(TCC0), pwm_chan1_config, ARRAY_SIZE(pwm_chan1_config), SAM0_GCLK_MAIN},
218 #endif
219 };
220 
221 /* number of devices that are actually defined */
222 #define PWM_NUMOF ARRAY_SIZE(pwm_config)
223 
229 static const spi_conf_t spi_config[] = {
230  {
231  .dev = &SERCOM4->SPI,
232  .miso_pin = GPIO_PIN(PC, 19),
233  .mosi_pin = GPIO_PIN(PB, 30),
234  .clk_pin = GPIO_PIN(PC, 18),
235  .miso_mux = GPIO_MUX_F,
236  .mosi_mux = GPIO_MUX_F,
237  .clk_mux = GPIO_MUX_F,
238  .miso_pad = SPI_PAD_MISO_0,
239  .mosi_pad = SPI_PAD_MOSI_2_SCK_3,
240  .gclk_src = SAM0_GCLK_MAIN,
241 #ifdef MODULE_PERIPH_DMA
242  .tx_trigger = SERCOM4_DMAC_ID_TX,
243  .rx_trigger = SERCOM4_DMAC_ID_RX,
244 #endif
245  },
246  {
247  .dev = &SERCOM5->SPI,
248  .miso_pin = GPIO_PIN(PB, 2),
249  .mosi_pin = GPIO_PIN(PB, 22),
250  .clk_pin = GPIO_PIN(PB, 23),
251  .miso_mux = GPIO_MUX_D,
252  .mosi_mux = GPIO_MUX_D,
253  .clk_mux = GPIO_MUX_D,
254  .miso_pad = SPI_PAD_MISO_0,
255  .mosi_pad = SPI_PAD_MOSI_2_SCK_3,
256  .gclk_src = SAM0_GCLK_MAIN,
257 #ifdef MODULE_PERIPH_DMA
258  .tx_trigger = SERCOM5_DMAC_ID_TX,
259  .rx_trigger = SERCOM5_DMAC_ID_RX,
260 #endif
261  }
262 };
263 
264 #define SPI_NUMOF ARRAY_SIZE(spi_config)
265 
271 static const i2c_conf_t i2c_config[] = {
272  {
273  .dev = &(SERCOM3->I2CM),
274  .speed = I2C_SPEED_NORMAL,
275  .scl_pin = GPIO_PIN(PA, 17),
276  .sda_pin = GPIO_PIN(PA, 16),
277  .mux = GPIO_MUX_D,
278  .gclk_src = SAM0_GCLK_MAIN,
279  .flags = I2C_FLAG_NONE
280  }
281 };
282 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
283 
289 #ifndef RTT_FREQUENCY
290 #define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
291 #endif
292 #define RTT_MIN_OFFSET (10U)
293 
300 /* ADC Default values */
301 #define ADC_PRESCALER ADC_CTRLB_PRESCALER_DIV512
302 
303 #define ADC_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
304 #define ADC_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
305 #define ADC_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
306 
307 static const adc_conf_chan_t adc_channels[] = {
308  /* port, pin, muxpos */
309  {GPIO_PIN(PA, 6), ADC_INPUTCTRL_MUXPOS_PIN6}, /* EXT1, pin 3 */
310  {GPIO_PIN(PA, 7), ADC_INPUTCTRL_MUXPOS_PIN7}, /* EXT1, pin 4 */
311 };
312 
313 #define ADC_NUMOF ARRAY_SIZE(adc_channels)
314 
320 static const sam0_common_usb_config_t sam_usbdev_config[] = {
321  {
322  .dm = GPIO_PIN(PA, 24),
323  .dp = GPIO_PIN(PA, 25),
324  .d_mux = GPIO_MUX_G,
325  .device = &USB->DEVICE,
326  .gclk_src = SAM0_GCLK_MAIN,
327  }
328 };
330 #ifdef __cplusplus
331 }
332 #endif
333 
334 #endif /* PERIPH_CONF_H */
335 
select peripheral function D
port B
Definition: periph_cpu.h:93
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
I2C configuration options.
Definition: periph_cpu.h:128
Tc * dev
pointer to the used Timer device
use pad 0 for MISO line
port C
Definition: periph_cpu.h:94
select peripheral function E
No flags set.
static const gpio_t adc_channels[]
Static array with declared ADC channels.
#define ARRAY_SIZE(a)
Calculate the number of elements in a static array.
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:458
select pad 1
select pad 0
select peripheral function F
gpio_t dm
D- line gpio.
No flags set.
ADC Channel Configuration.
PWM device configuration.
select peripheral function G
USB peripheral parameters.
PWM channel configuration data structure.
UART device configuration.
Definition: periph_cpu.h:166
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:246
port A
Definition: periph_cpu.h:92
use pad 2 for MOSI, pad 3 for SCK
SPI configuration structure type.
Definition: periph_cpu.h:273
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
TX is pad 0, on top RTS on pad 2 and CTS on pad 3.
normal mode: ~100 kbit/s
Definition: i2c.h:177
1 MHz clock for xTimer
Definition: periph_cpu.h:60
48 MHz main clock
Definition: periph_cpu.h:59
#define TCC_CONFIG(tim)
Static initializer for TCC timer configuration.
Timer device configuration.