boards/samd21-xpro/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Travis Griggs <travisgriggs@gmail.com>
3  * Copyright (C) 2017 Dan Evans <photonthunder@gmail.com>
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include <stdint.h>
26 
27 #include "cpu.h"
28 #include "periph_cpu.h"
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
66 #define CLOCK_USE_PLL (1)
67 
68 #if CLOCK_USE_PLL
69 /* edit these values to adjust the PLL output frequency */
70 #define CLOCK_PLL_MUL (47U) /* must be >= 31 & <= 95 */
71 #define CLOCK_PLL_DIV (1U) /* adjust to your needs */
72 /* generate the actual used core clock frequency */
73 #define CLOCK_CORECLOCK (((CLOCK_PLL_MUL + 1) * 1000000U) / CLOCK_PLL_DIV)
74 #elif CLOCK_USE_XOSC32_DFLL
75 /* Settings for 32 kHz external oscillator and 48 MHz DFLL */
76 #define CLOCK_CORECLOCK (48000000U)
77 #define CLOCK_XOSC32K (32768UL)
78 #define CLOCK_8MHZ (1)
79 #define GEN2_ULP32K (1)
80 #else
81 /* edit this value to your needs */
82 #define CLOCK_DIV (1U)
83 /* generate the actual core clock frequency */
84 #define CLOCK_CORECLOCK (8000000 / CLOCK_DIV)
85 #endif
86 
92 #define TIMER_NUMOF (2U)
93 #define TIMER_0_EN 1
94 #define TIMER_1_EN 1
95 
96 /* Timer 0 configuration */
97 #define TIMER_0_DEV TC3->COUNT16
98 #define TIMER_0_CHANNELS 2
99 #define TIMER_0_MAX_VALUE (0xffff)
100 #define TIMER_0_ISR isr_tc3
101 
102 /* Timer 1 configuration */
103 #define TIMER_1_DEV TC4->COUNT32
104 #define TIMER_1_CHANNELS 2
105 #define TIMER_1_MAX_VALUE (0xffffffff)
106 #define TIMER_1_ISR isr_tc4
107 
113 static const uart_conf_t uart_config[] = {
114  { /* Virtual COM Port */
115  .dev = &SERCOM3->USART,
116  .rx_pin = GPIO_PIN(PA,23),
117  .tx_pin = GPIO_PIN(PA,22),
118  .mux = GPIO_MUX_C,
119  .rx_pad = UART_PAD_RX_1,
120  .tx_pad = UART_PAD_TX_0,
121  .flags = UART_FLAG_NONE,
122  .gclk_src = GCLK_CLKCTRL_GEN_GCLK0
123  },
124  { /* EXT1 */
125  .dev = &SERCOM4->USART,
126  .rx_pin = GPIO_PIN(PB,9),
127  .tx_pin = GPIO_PIN(PB,8),
128  .mux = GPIO_MUX_D,
129  .rx_pad = UART_PAD_RX_1,
130  .tx_pad = UART_PAD_TX_0,
131  .flags = UART_FLAG_NONE,
132  .gclk_src = GCLK_CLKCTRL_GEN_GCLK0
133  },
134  { /* EXT2/3 */
135  .dev = &SERCOM4->USART,
136  .rx_pin = GPIO_PIN(PB,11),
137  .tx_pin = GPIO_PIN(PB,10),
138  .mux = GPIO_MUX_D,
139  .rx_pad = UART_PAD_RX_3,
140  .tx_pad = UART_PAD_TX_2,
141  .flags = UART_FLAG_NONE,
142  .gclk_src = GCLK_CLKCTRL_GEN_GCLK0
143  }
144 };
145 
146 /* interrupt function name mapping */
147 #define UART_0_ISR isr_sercom3
148 #define UART_1_ISR isr_sercom4
149 #define UART_2_ISR isr_sercom5
150 
151 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
152 
158 #define PWM_0_EN 1
159 #define PWM_1_EN 0
160 #define PWM_2_EN 0
161 #define PWM_MAX_CHANNELS 2
162 /* for compatibility with test application */
163 #define PWM_0_CHANNELS PWM_MAX_CHANNELS
164 #define PWM_1_CHANNELS PWM_MAX_CHANNELS
165 #define PWM_2_CHANNELS PWM_MAX_CHANNELS
166 
167 /* PWM device configuration */
168 static const pwm_conf_t pwm_config[] = {
169 #if PWM_0_EN
170  {TCC2, {
171  /* GPIO pin, MUX value, TCC channel */
172  { GPIO_PIN(PA, 12), GPIO_MUX_E, 0 },
173  { GPIO_PIN(PA, 13), GPIO_MUX_E, 1 },
174  }},
175 #endif
176 #if PWM_1_EN
177  {TC4, {
178  /* GPIO pin, MUX value, TCC channel */
179  { GPIO_PIN(PB, 12), GPIO_MUX_E, 0 },
180  { GPIO_PIN(PB, 13), GPIO_MUX_E, 1 },
181  }}
182 #endif
183 #if PWM_2_EN
184  {TC6, {
185  /* GPIO pin, MUX value, TCC channel */
186  { GPIO_PIN(PB, 02), GPIO_MUX_E, 0 },
187  { GPIO_PIN(PB, 03), GPIO_MUX_E, 1 },
188  }}
189 #endif
190 };
191 
192 /* number of devices that are actually defined */
193 #define PWM_NUMOF (3U)
194 
200 static const spi_conf_t spi_config[] = {
201  { /* EXT1 */
202  .dev = &SERCOM0->SPI,
203  .miso_pin = GPIO_PIN(PA, 4),
204  .mosi_pin = GPIO_PIN(PA, 6),
205  .clk_pin = GPIO_PIN(PA, 7),
206  .miso_mux = GPIO_MUX_D,
207  .mosi_mux = GPIO_MUX_D,
208  .clk_mux = GPIO_MUX_D,
209  .miso_pad = SPI_PAD_MISO_0,
210  .mosi_pad = SPI_PAD_MOSI_2_SCK_3
211  },
212  { /* EXT2 */
213  .dev = &SERCOM1->SPI,
214  .miso_pin = GPIO_PIN(PA, 16),
215  .mosi_pin = GPIO_PIN(PA, 18),
216  .clk_pin = GPIO_PIN(PA, 19),
217  .miso_mux = GPIO_MUX_C,
218  .mosi_mux = GPIO_MUX_C,
219  .clk_mux = GPIO_MUX_C,
220  .miso_pad = SPI_PAD_MISO_0,
221  .mosi_pad = SPI_PAD_MOSI_2_SCK_3
222  },
223  { /* EXT3 */
224  .dev = &SERCOM5->SPI,
225  .miso_pin = GPIO_PIN(PB, 16),
226  .mosi_pin = GPIO_PIN(PB, 22),
227  .clk_pin = GPIO_PIN(PB, 23),
228  .miso_mux = GPIO_MUX_C,
229  .mosi_mux = GPIO_MUX_D,
230  .clk_mux = GPIO_MUX_D,
231  .miso_pad = SPI_PAD_MISO_0,
232  .mosi_pad = SPI_PAD_MOSI_2_SCK_3
233  }
234 };
235 
236 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
237 
243 #define I2C_NUMOF (1U)
244 #define I2C_0_EN 1
245 #define I2C_1_EN 0
246 #define I2C_2_EN 0
247 #define I2C_3_EN 0
248 #define I2C_IRQ_PRIO 1
249 
250 #define I2C_0_DEV SERCOM2->I2CM
251 #define I2C_0_IRQ SERCOM2_IRQn
252 #define I2C_0_ISR isr_sercom2
253 /* I2C 0 GCLK */
254 #define I2C_0_GCLK_ID SERCOM2_GCLK_ID_CORE
255 #define I2C_0_GCLK_ID_SLOW SERCOM2_GCLK_ID_SLOW
256 /* I2C 0 pin configuration */
257 #define I2C_0_SDA GPIO_PIN(PA, 8)
258 #define I2C_0_SCL GPIO_PIN(PA, 9)
259 #define I2C_0_MUX GPIO_MUX_D
260 
265 #define RTC_NUMOF (1U)
266 #define RTC_DEV RTC->MODE2
267 
273 #define RTT_NUMOF (1U)
274 #define RTT_DEV RTC->MODE0
275 #define RTT_IRQ RTC_IRQn
276 #define RTT_IRQ_PRIO 10
277 #define RTT_ISR isr_rtc
278 #define RTT_MAX_VALUE (0xffffffff)
279 #define RTT_FREQUENCY (32768U) /* in Hz. For changes see `rtt.c` */
280 #define RTT_RUNSTDBY (1) /* Keep RTT running in sleep states */
281 
287 #define ADC_0_EN 1
288 #define ADC_MAX_CHANNELS 14
289 /* ADC 0 device configuration */
290 #define ADC_0_DEV ADC
291 #define ADC_0_IRQ ADC_IRQn
292 
293 /* ADC 0 Default values */
294 #define ADC_0_CLK_SOURCE 0 /* GCLK_GENERATOR_0 */
295 #define ADC_0_PRESCALER ADC_CTRLB_PRESCALER_DIV512
296 
297 #define ADC_0_NEG_INPUT ADC_INPUTCTRL_MUXNEG_GND
298 #define ADC_0_GAIN_FACTOR_DEFAULT ADC_INPUTCTRL_GAIN_1X
299 #define ADC_0_REF_DEFAULT ADC_REFCTRL_REFSEL_INT1V
300 
301 static const adc_conf_chan_t adc_channels[] = {
302  /* port, pin, muxpos */
303  {GPIO_PIN(PB, 0), ADC_INPUTCTRL_MUXPOS_PIN8}, /* EXT1, pin 3 */
304  {GPIO_PIN(PB, 1), ADC_INPUTCTRL_MUXPOS_PIN9}, /* EXT1, pin 4 */
305  {GPIO_PIN(PA, 10), ADC_INPUTCTRL_MUXPOS_PIN18}, /* EXT2, pin 3 */
306  {GPIO_PIN(PA, 11), ADC_INPUTCTRL_MUXPOS_PIN19}, /* EXT2, pin 4 */
307  {GPIO_PIN(PA, 2), ADC_INPUTCTRL_MUXPOS_PIN0}, /* EXT3, pin 3 */
308  {GPIO_PIN(PA, 3), ADC_INPUTCTRL_MUXPOS_PIN1} /* EXT3, pin 4. This is
309  disconnected by default. PA3 is connected to USB_ID.
310  Move PA03 SELECT jumper to EXT3 to connect. */
311 };
312 
313 #define ADC_0_CHANNELS (6U)
314 #define ADC_NUMOF ADC_0_CHANNELS
315 
317 #ifdef __cplusplus
318 }
319 #endif
320 
321 #endif /* PERIPH_CONF_H */
322 
select peripheral function D
void * dev
UART, USART or LEUART device used.
select peripheral function E
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
ADC Channel Configuration.
PWM device configuration.
select peripheral function C
UART device configuration.
use pad 2 for MOSI, pad 3 for SCK
SPI module configuration options.
cc2538_ssi_t * dev
SSI device.