periph_conf.h
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1 /*
2  * Copyright (C) 2019 Inria
3  * 2019 Freie Universit├Ąt Berln
4  * 2019 Kaspar Schleiser <kaspar@schleiser.de>
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 #include "cfg_usb_otg_fs.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
38 /* give the target core clock (HCLK) frequency [in Hz],
39  * maximum: 168MHz */
40 #define CLOCK_CORECLOCK (168000000U)
41 /* 0: no external high speed crystal available
42  * else: actual crystal frequency [in Hz] */
43 #define CLOCK_HSE (12000000U)
44 /* 0: no external low speed crystal available,
45  * 1: external crystal available (always 32.768kHz) */
46 #define CLOCK_LSE (1U)
47 /* peripheral clock setup */
48 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
49 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
50 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
51 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
52 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
53 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
54 
55 /* Main PLL factors */
56 #define CLOCK_PLL_M (6)
57 #define CLOCK_PLL_N (168)
58 #define CLOCK_PLL_P (2)
59 #define CLOCK_PLL_Q (7)
60 
66 static const dma_conf_t dma_config[] = {
67  { .stream = 11 }, /* DMA2 Stream 3 - SPI1_TX */
68  { .stream = 10 }, /* DMA2 Stream 2 - SPI1_RX */
69 };
70 
71 #define DMA_0_ISR isr_dma2_stream3
72 #define DMA_1_ISR isr_dma2_stream2
73 
74 #define DMA_NUMOF ARRAY_SIZE(dma_config)
75 
81 static const timer_conf_t timer_config[] = {
82  {
83  .dev = TIM5,
84  .max = 0xffffffff,
85  .rcc_mask = RCC_APB1ENR_TIM5EN,
86  .bus = APB1,
87  .irqn = TIM5_IRQn
88  }
89 };
90 
91 #define TIMER_0_ISR isr_tim5
92 
93 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
94 
100 static const uart_conf_t uart_config[] = {
101  {
102  .dev = USART1,
103  .rcc_mask = RCC_APB2ENR_USART1EN,
104  .rx_pin = GPIO_PIN(PORT_B, 7),
105  .tx_pin = GPIO_PIN(PORT_B, 6),
106  .rx_af = GPIO_AF7,
107  .tx_af = GPIO_AF7,
108  .bus = APB2,
109  .irqn = USART1_IRQn,
110 #ifdef MODULE_PERIPH_DMA
111  .dma = DMA_STREAM_UNDEF,
112  .dma_chan = UINT8_MAX,
113 #endif
114  },
115 };
116 
117 #define UART_0_ISR (isr_usart1)
118 
119 #define UART_NUMOF ARRAY_SIZE(uart_config)
120 
129 static const uint8_t spi_divtable[2][5] = {
130  { /* for APB1 @ 42000000Hz */
131  7, /* -> 164062Hz */
132  6, /* -> 328125Hz */
133  4, /* -> 1312500Hz */
134  2, /* -> 5250000Hz */
135  1 /* -> 10500000Hz */
136  },
137  { /* for APB2 @ 84000000Hz */
138  7, /* -> 328125Hz */
139  7, /* -> 328125Hz */
140  5, /* -> 1312500Hz */
141  3, /* -> 5250000Hz */
142  2 /* -> 10500000Hz */
143  }
144 };
145 
146 static const spi_conf_t spi_config[] = {
147  {
148  .dev = SPI1,
149  .mosi_pin = GPIO_PIN(PORT_A, 7),
150  .miso_pin = GPIO_PIN(PORT_A, 6),
151  .sclk_pin = GPIO_PIN(PORT_A, 5),
152  .cs_pin = GPIO_UNDEF,
153  .mosi_af = GPIO_AF5,
154  .miso_af = GPIO_AF5,
155  .sclk_af = GPIO_AF5,
156  .cs_af = GPIO_AF5,
157  .rccmask = RCC_APB2ENR_SPI1EN,
158  .apbbus = APB2,
159 #ifdef MODULE_PERIPH_DMA
160  .tx_dma = 0,
161  .tx_dma_chan = 3,
162  .rx_dma = 1,
163  .rx_dma_chan = 3,
164 #endif
165  }
166 };
167 
168 #define SPI_NUMOF ARRAY_SIZE(spi_config)
169 
175 static const i2c_conf_t i2c_config[] = {
176  {
177  .dev = I2C2,
178  .speed = I2C_SPEED_NORMAL,
179  .scl_pin = GPIO_PIN(PORT_B, 10),
180  .sda_pin = GPIO_PIN(PORT_B, 11),
181  .scl_af = GPIO_AF4,
182  .sda_af = GPIO_AF4,
183  .bus = APB1,
184  .rcc_mask = RCC_APB1ENR_I2C2EN,
185  .clk = CLOCK_APB1,
186  .irqn = I2C2_ER_IRQn,
187  },
188 };
189 
190 #define I2C_0_ISR isr_i2c2_er
191 
192 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
193 
195 #ifdef __cplusplus
196 }
197 #endif
198 
199 #endif /* PERIPH_CONF_H */
200 
DMA configuration.
Definition: periph_cpu.h:395
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
I2C configuration options.
Definition: periph_cpu.h:128
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:458
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
NRF_TIMER_Type * dev
timer device
Common configuration for STM32 OTG FS peripheral.
use alternate function 5
port A
Definition: periph_cpu.h:36
use alternate function 4
APB1 bus.
Definition: periph_cpu.h:167
UART device configuration.
Definition: periph_cpu.h:166
APB2 bus.
Definition: periph_cpu.h:168
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:240
static const uint8_t spi_divtable[2][5]
Shared SPI clock div table.
Definition: periph_conf.h:161
int stream
DMA stream on stm32f2/4/7, channel on others STM32F2/4/7:
Definition: periph_cpu.h:418
SPI configuration structure type.
Definition: periph_cpu.h:273
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
normal mode: ~100 kbit/s
Definition: i2c.h:183
Timer configuration.
Definition: periph_cpu.h:288
use alternate function 7
port B
Definition: periph_cpu.h:37