periph_conf.h
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1 /*
2  * Copyright (C) 2019 Inria
3  * 2019 Freie Universit├Ąt Berln
4  * 2019 Kaspar Schleiser <kaspar@schleiser.de>
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 168MHz */
39 #define CLOCK_CORECLOCK (168000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (12000000U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (1U)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
53 
54 /* Main PLL factors */
55 #define CLOCK_PLL_M (6)
56 #define CLOCK_PLL_N (168)
57 #define CLOCK_PLL_P (2)
58 #define CLOCK_PLL_Q (7)
59 
65 static const timer_conf_t timer_config[] = {
66  {
67  .dev = TIM5,
68  .max = 0xffffffff,
69  .rcc_mask = RCC_APB1ENR_TIM5EN,
70  .bus = APB1,
71  .irqn = TIM5_IRQn
72  }
73 };
74 
75 #define TIMER_0_ISR isr_tim5
76 
77 #define TIMER_NUMOF ARRAY_SIZE(timer_config)
78 
84 static const uart_conf_t uart_config[] = {
85  {
86  .dev = USART1,
87  .rcc_mask = RCC_APB2ENR_USART1EN,
88  .rx_pin = GPIO_PIN(PORT_B, 7),
89  .tx_pin = GPIO_PIN(PORT_B, 6),
90  .rx_af = GPIO_AF7,
91  .tx_af = GPIO_AF7,
92  .bus = APB2,
93  .irqn = USART1_IRQn,
94 #ifdef MODULE_PERIPH_DMA
95  .dma = 2,
96  .dma_chan = 2
97 #endif
98  },
99 };
100 
101 #define UART_0_ISR (isr_usart1)
102 
103 #define UART_NUMOF ARRAY_SIZE(uart_config)
104 
113 static const uint8_t spi_divtable[2][5] = {
114  { /* for APB1 @ 42000000Hz */
115  7, /* -> 164062Hz */
116  6, /* -> 328125Hz */
117  4, /* -> 1312500Hz */
118  2, /* -> 5250000Hz */
119  1 /* -> 10500000Hz */
120  },
121  { /* for APB2 @ 84000000Hz */
122  7, /* -> 328125Hz */
123  7, /* -> 328125Hz */
124  5, /* -> 1312500Hz */
125  3, /* -> 5250000Hz */
126  2 /* -> 10500000Hz */
127  }
128 };
129 
130 static const spi_conf_t spi_config[] = {
131  {
132  .dev = SPI1,
133  .mosi_pin = GPIO_PIN(PORT_A, 7),
134  .miso_pin = GPIO_PIN(PORT_A, 6),
135  .sclk_pin = GPIO_PIN(PORT_A, 5),
136  .cs_pin = GPIO_UNDEF,
137  .mosi_af = GPIO_AF5,
138  .miso_af = GPIO_AF5,
139  .sclk_af = GPIO_AF5,
140  .cs_af = GPIO_AF5,
141  .rccmask = RCC_APB2ENR_SPI1EN,
142  .apbbus = APB2,
143 #ifdef MODULE_PERIPH_DMA
144  .tx_dma = 1,
145  .tx_dma_chan = 1,
146  .rx_dma = 0,
147  .rx_dma_chan = 1,
148 #endif
149  }
150 };
151 
152 #define SPI_NUMOF ARRAY_SIZE(spi_config)
153 
159 static const i2c_conf_t i2c_config[] = {
160  {
161  .dev = I2C2,
162  .speed = I2C_SPEED_NORMAL,
163  .scl_pin = GPIO_PIN(PORT_B, 10),
164  .sda_pin = GPIO_PIN(PORT_B, 11),
165  .scl_af = GPIO_AF4,
166  .sda_af = GPIO_AF4,
167  .bus = APB1,
168  .rcc_mask = RCC_APB1ENR_I2C2EN,
169  .clk = CLOCK_APB1,
170  .irqn = I2C2_ER_IRQn,
171  },
172 };
173 
174 #define I2C_0_ISR isr_i2c2_er
175 
176 #define I2C_NUMOF ARRAY_SIZE(i2c_config)
177 
179 #ifdef __cplusplus
180 }
181 #endif
182 
183 #endif /* PERIPH_CONF_H */
184 
use alternate function 4
use alternate function 7
cc2538_uart_t * dev
pointer to the used UART device
Definition: periph_cpu.h:167
I2C configuration options.
Definition: periph_cpu.h:128
APB1 bus.
SPI_Type * dev
SPI device to use.
Definition: periph_cpu.h:435
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
NRF_TIMER_Type * dev
timer device
port A
Definition: periph_cpu.h:36
APB2 bus.
use alternate function 5
UART device configuration.
Definition: periph_cpu.h:166
I2C_TypeDef * dev
USART device used.
Definition: periph_cpu.h:240
static const uint8_t spi_divtable[2][5]
Shared SPI clock div table.
Definition: periph_conf.h:166
SPI configuration structure type.
Definition: periph_cpu.h:271
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition: periph_cpu.h:35
normal mode: ~100 kbit/s
Definition: i2c.h:183
Timer configuration.
Definition: periph_cpu.h:286
port B
Definition: periph_cpu.h:37