boards/nucleo32-l432/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * 2017 OTA keys
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 /* 0: no external high speed crystal available
34  * else: actual crystal frequency [in Hz] */
35 #define CLOCK_HSE (0)
36 /* 0: no external low speed crystal available,
37  * 1: external crystal available (always 32.768kHz) */
38 #define CLOCK_LSE (1)
39 /* 0: enable MSI only if HSE isn't available
40  * 1: always enable MSI (e.g. if USB or RNG is used)*/
41 #define CLOCK_MSI_ENABLE (1)
42 /* 0: disable Hardware auto calibration with LSE
43  * 1: enable Hardware auto calibration with LSE (PLL-mode)*/
44 #define CLOCK_MSI_LSE_PLL (1)
45 /* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
46 #define CLOCK_CORECLOCK (80000000U)
47 /* PLL configuration: make sure your values are legit!
48  *
49  * compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
50  * with:
51  * PLL_IN: input clock, HSE or MSI @ 48MHz
52  * M: pre-divider, allowed range: [1:8]
53  * N: multiplier, allowed range: [8:86]
54  * R: post-divider, allowed range: [2,4,6,8]
55  *
56  * Also the following constraints need to be met:
57  * (PLL_IN / M) -> [4MHz:16MHz]
58  * (PLL_IN / M) * N -> [64MHz:344MHz]
59  * CORECLOCK -> 80MHz MAX!
60  */
61 #define CLOCK_PLL_M (6)
62 #define CLOCK_PLL_N (20)
63 #define CLOCK_PLL_R (2)
64 /* peripheral clock setup */
65 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
66 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
67 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
68 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
69 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
70 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
71 
77 static const timer_conf_t timer_config[] = {
78  {
79  .dev = TIM2,
80  .max = 0xffffffff,
81  .rcc_mask = RCC_APB1ENR1_TIM2EN,
82  .bus = APB1,
83  .irqn = TIM2_IRQn
84  }
85 };
86 
87 #define TIMER_0_ISR isr_tim2
88 
89 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
90 
96 static const uart_conf_t uart_config[] = {
97  {
98  .dev = USART2,
99  .rcc_mask = RCC_APB1ENR1_USART2EN,
100  .rx_pin = GPIO_PIN(PORT_A, 15),
101  .tx_pin = GPIO_PIN(PORT_A, 2),
102  .rx_af = GPIO_AF3,
103  .tx_af = GPIO_AF7,
104  .bus = APB1,
105  .irqn = USART2_IRQn
106  },
107  {
108  .dev = USART1,
109  .rcc_mask = RCC_APB2ENR_USART1EN,
110  .rx_pin = GPIO_PIN(PORT_A, 10),
111  .tx_pin = GPIO_PIN(PORT_A, 9),
112  .rx_af = GPIO_AF7,
113  .tx_af = GPIO_AF7,
114  .bus = APB2,
115  .irqn = USART1_IRQn
116  },
117 };
118 
119 #define UART_0_ISR (isr_usart2)
120 #define UART_1_ISR (isr_usart1)
121 
122 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
123 
129 static const pwm_conf_t pwm_config[] = {
130  {
131  .dev = TIM1,
132  .rcc_mask = RCC_APB2ENR_TIM1EN,
133  .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
134  { .pin = GPIO_UNDEF, .cc_chan = 0 },
135  { .pin = GPIO_UNDEF, .cc_chan = 0 },
136  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
137  .af = GPIO_AF1,
138  .bus = APB2
139  }
140 };
141 
142 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
143 
152 static const uint8_t spi_divtable[2][5] = {
153  { /* for APB1 @ 20000000Hz */
154  7, /* -> 78125Hz */
155  5, /* -> 312500Hz */
156  3, /* -> 1250000Hz */
157  1, /* -> 5000000Hz */
158  0 /* -> 10000000Hz */
159  },
160  { /* for APB2 @ 40000000Hz */
161  7, /* -> 156250Hz */
162  6, /* -> 312500Hz */
163  4, /* -> 1250000Hz */
164  2, /* -> 5000000Hz */
165  1 /* -> 10000000Hz */
166  }
167 };
168 
169 static const spi_conf_t spi_config[] = {
170  {
171  .dev = SPI1,
172  .mosi_pin = GPIO_PIN(PORT_B, 5),
173  .miso_pin = GPIO_PIN(PORT_B, 4),
174  .sclk_pin = GPIO_PIN(PORT_B, 3),
175  .cs_pin = GPIO_UNDEF,
176  .af = GPIO_AF5,
177  .rccmask = RCC_APB2ENR_SPI1EN,
178  .apbbus = APB2
179  }
180 };
181 
182 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
183 
189 #define RTC_NUMOF (0U)
190 
196 #define ADC_NUMOF (0U)
197 
199 #ifdef __cplusplus
200 }
201 #endif
202 
203 #endif /* PERIPH_CONF_H */
204 
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 3
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
cc2538_ssi_t * dev
SSI device.