boards/nucleo32-l432/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * 2017 OTA keys
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 /* 0: no external high speed crystal available
34  * else: actual crystal frequency [in Hz] */
35 #define CLOCK_HSE (0)
36 /* 0: no external low speed crystal available,
37  * 1: external crystal available (always 32.768kHz) */
38 #define CLOCK_LSE (1)
39 /* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
40 #define CLOCK_CORECLOCK (80000000U)
41 /* PLL configuration: make sure your values are legit!
42  *
43  * compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
44  * with:
45  * PLL_IN: input clock, HSE or MSI @ 48MHz
46  * M: pre-divider, allowed range: [1:8]
47  * N: multiplier, allowed range: [8:86]
48  * R: post-divider, allowed range: [2,4,6,8]
49  *
50  * Also the following constraints need to be met:
51  * (PLL_IN / M) -> [4MHz:16MHz]
52  * (PLL_IN / M) * N -> [64MHz:344MHz]
53  * CORECLOCK -> 80MHz MAX!
54  */
55 #define CLOCK_PLL_M (6)
56 #define CLOCK_PLL_N (20)
57 #define CLOCK_PLL_R (2)
58 /* peripheral clock setup */
59 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
60 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
61 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
62 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
63 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
64 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
65 
71 static const timer_conf_t timer_config[] = {
72  {
73  .dev = TIM2,
74  .max = 0xffffffff,
75  .rcc_mask = RCC_APB1ENR1_TIM2EN,
76  .bus = APB1,
77  .irqn = TIM2_IRQn
78  }
79 };
80 
81 #define TIMER_0_ISR isr_tim2
82 
83 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
84 
90 static const uart_conf_t uart_config[] = {
91  {
92  .dev = USART2,
93  .rcc_mask = RCC_APB1ENR1_USART2EN,
94  .rx_pin = GPIO_PIN(PORT_A, 15),
95  .tx_pin = GPIO_PIN(PORT_A, 2),
96  .rx_af = GPIO_AF3,
97  .tx_af = GPIO_AF7,
98  .bus = APB1,
99  .irqn = USART2_IRQn
100  },
101  {
102  .dev = USART1,
103  .rcc_mask = RCC_APB2ENR_USART1EN,
104  .rx_pin = GPIO_PIN(PORT_A, 10),
105  .tx_pin = GPIO_PIN(PORT_A, 9),
106  .rx_af = GPIO_AF7,
107  .tx_af = GPIO_AF7,
108  .bus = APB2,
109  .irqn = USART1_IRQn
110  },
111 };
112 
113 #define UART_0_ISR (isr_usart2)
114 #define UART_1_ISR (isr_usart1)
115 
116 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
117 
123 static const pwm_conf_t pwm_config[] = {
124  {
125  .dev = TIM1,
126  .rcc_mask = RCC_APB2ENR_TIM1EN,
127  .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
128  { .pin = GPIO_UNDEF, .cc_chan = 0 },
129  { .pin = GPIO_UNDEF, .cc_chan = 0 },
130  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
131  .af = GPIO_AF1,
132  .bus = APB2
133  }
134 };
135 
136 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
137 
146 static const uint8_t spi_divtable[2][5] = {
147  { /* for APB1 @ 20000000Hz */
148  7, /* -> 78125Hz */
149  5, /* -> 312500Hz */
150  3, /* -> 1250000Hz */
151  1, /* -> 5000000Hz */
152  0 /* -> 10000000Hz */
153  },
154  { /* for APB2 @ 40000000Hz */
155  7, /* -> 156250Hz */
156  6, /* -> 312500Hz */
157  4, /* -> 1250000Hz */
158  2, /* -> 5000000Hz */
159  1 /* -> 10000000Hz */
160  }
161 };
162 
163 static const spi_conf_t spi_config[] = {
164  {
165  .dev = SPI1,
166  .mosi_pin = GPIO_PIN(PORT_B, 5),
167  .miso_pin = GPIO_PIN(PORT_B, 4),
168  .sclk_pin = GPIO_PIN(PORT_B, 3),
169  .cs_pin = GPIO_UNDEF,
170  .af = GPIO_AF5,
171  .rccmask = RCC_APB2ENR_SPI1EN,
172  .apbbus = APB2
173  }
174 };
175 
176 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
177 
183 #define RTC_NUMOF (0U)
184 
190 #define ADC_NUMOF (0U)
191 
197 #define DAC_NUMOF (0U)
198 
200 #ifdef __cplusplus
201 }
202 #endif
203 
204 #endif /* PERIPH_CONF_H */
205 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 3
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.