boards/nucleo32-l432/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * 2017 OTA keys
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
23 #ifndef PERIPH_CONF_H
24 #define PERIPH_CONF_H
25 
26 #include "periph_cpu.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 /* 0: no external high speed crystal available
37  * else: actual crystal frequency [in Hz] */
38 #define CLOCK_HSE (0)
39 /* 0: no external low speed crystal available,
40  * 1: external crystal available (always 32.768kHz) */
41 #define CLOCK_LSE (1)
42 /* 0: enable MSI only if HSE isn't available
43  * 1: always enable MSI (e.g. if USB or RNG is used)*/
44 #define CLOCK_MSI_ENABLE (1)
45 /* 0: disable Hardware auto calibration with LSE
46  * 1: enable Hardware auto calibration with LSE (PLL-mode)*/
47 #define CLOCK_MSI_LSE_PLL (1)
48 /* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
49 #define CLOCK_CORECLOCK (80000000U)
50 /* PLL configuration: make sure your values are legit!
51  *
52  * compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
53  * with:
54  * PLL_IN: input clock, HSE or MSI @ 48MHz
55  * M: pre-divider, allowed range: [1:8]
56  * N: multiplier, allowed range: [8:86]
57  * R: post-divider, allowed range: [2,4,6,8]
58  *
59  * Also the following constraints need to be met:
60  * (PLL_IN / M) -> [4MHz:16MHz]
61  * (PLL_IN / M) * N -> [64MHz:344MHz]
62  * CORECLOCK -> 80MHz MAX!
63  */
64 #define CLOCK_PLL_M (6)
65 #define CLOCK_PLL_N (20)
66 #define CLOCK_PLL_R (2)
67 /* peripheral clock setup */
68 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
69 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
70 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
71 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
72 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
73 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
74 
80 static const timer_conf_t timer_config[] = {
81  {
82  .dev = TIM2,
83  .max = 0xffffffff,
84  .rcc_mask = RCC_APB1ENR1_TIM2EN,
85  .bus = APB1,
86  .irqn = TIM2_IRQn
87  }
88 };
89 
90 #define TIMER_0_ISR isr_tim2
91 
92 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
93 
99 static const uart_conf_t uart_config[] = {
100  {
101  .dev = USART2,
102  .rcc_mask = RCC_APB1ENR1_USART2EN,
103  .rx_pin = GPIO_PIN(PORT_A, 15),
104  .tx_pin = GPIO_PIN(PORT_A, 2),
105  .rx_af = GPIO_AF3,
106  .tx_af = GPIO_AF7,
107  .bus = APB1,
108  .irqn = USART2_IRQn
109  },
110  {
111  .dev = USART1,
112  .rcc_mask = RCC_APB2ENR_USART1EN,
113  .rx_pin = GPIO_PIN(PORT_A, 10),
114  .tx_pin = GPIO_PIN(PORT_A, 9),
115  .rx_af = GPIO_AF7,
116  .tx_af = GPIO_AF7,
117  .bus = APB2,
118  .irqn = USART1_IRQn
119  },
120 };
121 
122 #define UART_0_ISR (isr_usart2)
123 #define UART_1_ISR (isr_usart1)
124 
125 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
126 
132 static const pwm_conf_t pwm_config[] = {
133  {
134  .dev = TIM1,
135  .rcc_mask = RCC_APB2ENR_TIM1EN,
136  .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
137  { .pin = GPIO_UNDEF, .cc_chan = 0 },
138  { .pin = GPIO_UNDEF, .cc_chan = 0 },
139  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
140  .af = GPIO_AF1,
141  .bus = APB2
142  }
143 };
144 
145 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
146 
155 static const uint8_t spi_divtable[2][5] = {
156  { /* for APB1 @ 20000000Hz */
157  7, /* -> 78125Hz */
158  5, /* -> 312500Hz */
159  3, /* -> 1250000Hz */
160  1, /* -> 5000000Hz */
161  0 /* -> 10000000Hz */
162  },
163  { /* for APB2 @ 40000000Hz */
164  7, /* -> 156250Hz */
165  6, /* -> 312500Hz */
166  4, /* -> 1250000Hz */
167  2, /* -> 5000000Hz */
168  1 /* -> 10000000Hz */
169  }
170 };
171 
172 static const spi_conf_t spi_config[] = {
173  {
174  .dev = SPI1,
175  .mosi_pin = GPIO_PIN(PORT_B, 5),
176  .miso_pin = GPIO_PIN(PORT_B, 4),
177  .sclk_pin = GPIO_PIN(PORT_B, 3),
178  .cs_pin = GPIO_UNDEF,
179  .af = GPIO_AF5,
180  .rccmask = RCC_APB2ENR_SPI1EN,
181  .apbbus = APB2
182  }
183 };
184 
185 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
186 
192 #define RTC_NUMOF (0U)
193 
199 #define ADC_NUMOF (0U)
200 
202 #ifdef __cplusplus
203 }
204 #endif
205 
206 #endif /* PERIPH_CONF_H */
207 
use alternate function 7
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
use alternate function 3
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
cc2538_ssi_t * dev
SSI device.