boards/nucleo32-l031/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Freie Universit├Ąt Berlin
3  * 2017 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
23 #ifndef PERIPH_CONF_H
24 #define PERIPH_CONF_H
25 
26 #include "periph_cpu.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 #define CLOCK_HSI (16000000U) /* internal oscillator */
37 #define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
38 
39 /* configuration of PLL prescaler and multiply values */
40 /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
41 #define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
42 #define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
43 /* configuration of peripheral bus clock prescalers */
44 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
45 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
46 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
47 /* configuration of flash access cycles */
48 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
49 
50 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
51 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
53 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
54 
60 static const timer_conf_t timer_config[] = {
61  {
62  .dev = TIM2,
63  .max = 0x0000ffff,
64  .rcc_mask = RCC_APB1ENR_TIM2EN,
65  .bus = APB1,
66  .irqn = TIM2_IRQn
67  }
68 };
69 
70 #define TIMER_0_ISR isr_tim2
71 
72 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
73 
79 static const uart_conf_t uart_config[] = {
80  {
81  .dev = USART2,
82  .rcc_mask = RCC_APB1ENR_USART2EN,
83  .rx_pin = GPIO_PIN(PORT_A, 15),
84  .tx_pin = GPIO_PIN(PORT_A, 2),
85  .rx_af = GPIO_AF4,
86  .tx_af = GPIO_AF4,
87  .bus = APB1,
88  .irqn = USART2_IRQn
89  }
90 };
91 
92 #define UART_0_ISR (isr_usart2)
93 
94 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
95 
101 static const pwm_conf_t pwm_config[] = {
102  {
103  .dev = TIM21,
104  .rcc_mask = RCC_APB2ENR_TIM21EN,
105  .chan = { { .pin = GPIO_PIN(PORT_B, 6) /* D5 */, .cc_chan = 0 },
106  { .pin = GPIO_UNDEF, .cc_chan = 0 },
107  { .pin = GPIO_UNDEF, .cc_chan = 0 },
108  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
109  .af = GPIO_AF5,
110  .bus = APB2
111  }
112 };
113 
114 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
115 
121 static const uint8_t spi_divtable[2][5] = {
122  { /* for APB1 @ 32000000Hz */
123  7, /* -> 125000Hz */
124  5, /* -> 500000Hz */
125  4, /* -> 1000000Hz */
126  2, /* -> 4000000Hz */
127  1 /* -> 8000000Hz */
128  },
129  { /* for APB2 @ 32000000Hz */
130  7, /* -> 125000Hz */
131  5, /* -> 500000Hz */
132  4, /* -> 1000000Hz */
133  2, /* -> 4000000Hz */
134  1 /* -> 8000000Hz */
135  }
136 };
137 
138 static const spi_conf_t spi_config[] = {
139  {
140  .dev = SPI1,
141  .mosi_pin = GPIO_PIN(PORT_B, 5),
142  .miso_pin = GPIO_PIN(PORT_B, 4),
143  .sclk_pin = GPIO_PIN(PORT_B, 3),
144  .cs_pin = GPIO_UNDEF,
145  .af = GPIO_AF0,
146  .rccmask = RCC_APB2ENR_SPI1EN,
147  .apbbus = APB2
148  }
149 };
150 
151 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
152 
158 #define ADC_CONFIG { \
159  { GPIO_PIN(PORT_A, 0), 0 }, /* Pin A0 */ \
160  { GPIO_PIN(PORT_A, 1), 1 }, /* Pin A1 */ \
161  { GPIO_PIN(PORT_A, 3), 3 }, /* Pin A2 */ \
162  { GPIO_PIN(PORT_A, 4), 4 }, /* Pin A3 */ \
163  { GPIO_PIN(PORT_A, 5), 5 }, /* Pin A4 */ \
164  { GPIO_PIN(PORT_A, 6), 6 }, /* Pin A5 */ \
165  { GPIO_PIN(PORT_A, 7), 7 }, /* Pin A6 */ \
166 }
167 #define ADC_NUMOF (7U)
168 
174 #define RTC_NUMOF (1U)
175 
177 #ifdef __cplusplus
178 }
179 #endif
180 
181 #endif /* PERIPH_CONF_H */
182 
use alternate function 4
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 0
use alternate function 5
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
cc2538_ssi_t * dev
SSI device.