boards/nucleo32-f303/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 72MHz */
39 #define CLOCK_CORECLOCK (64000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (0U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (0)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
53 
54 /* PLL factors */
55 #define CLOCK_PLL_PREDIV (2)
56 #define CLOCK_PLL_MUL (16)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM2,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM2EN,
68  .bus = APB1,
69  .irqn = TIM2_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim2
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART2,
85  .rcc_mask = RCC_APB1ENR_USART2EN,
86  .rx_pin = GPIO_PIN(PORT_A, 15),
87  .tx_pin = GPIO_PIN(PORT_A, 2),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB1,
91  .irqn = USART2_IRQn
92  },
93  {
94  .dev = USART1,
95  .rcc_mask = RCC_APB2ENR_USART1EN,
96  .rx_pin = GPIO_PIN(PORT_A, 10),
97  .tx_pin = GPIO_PIN(PORT_A, 9),
98  .rx_af = GPIO_AF7,
99  .tx_af = GPIO_AF7,
100  .bus = APB2,
101  .irqn = USART1_IRQn
102  }
103 };
104 
105 #define UART_0_ISR (isr_usart2)
106 #define UART_1_ISR (isr_usart1)
107 
108 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
109 
115 static const pwm_conf_t pwm_config[] = {
116  {
117  .dev = TIM3,
118  .rcc_mask = RCC_APB1ENR_TIM3EN,
119  .chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 },
120  { .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 3 },
121  { .pin = GPIO_UNDEF, .cc_chan = 0 },
122  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
123  .af = GPIO_AF2,
124  .bus = APB1
125  },
126  {
127  .dev = TIM1,
128  .rcc_mask = RCC_APB2ENR_TIM1EN,
129  .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
130  { .pin = GPIO_UNDEF, .cc_chan = 0 },
131  { .pin = GPIO_UNDEF, .cc_chan = 0 },
132  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
133  .af = GPIO_AF6,
134  .bus = APB2
135  }
136 };
137 
138 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
139 
148 static const uint8_t spi_divtable[2][5] = {
149  { /* for APB1 @ 32000000Hz */
150  7, /* -> 125000Hz */
151  5, /* -> 500000Hz */
152  4, /* -> 1000000Hz */
153  2, /* -> 4000000Hz */
154  1 /* -> 8000000Hz */
155  },
156  { /* for APB2 @ 64000000Hz */
157  7, /* -> 250000Hz */
158  6, /* -> 500000Hz */
159  5, /* -> 1000000Hz */
160  3, /* -> 4000000Hz */
161  2 /* -> 8000000Hz */
162  }
163 };
164 
165 static const spi_conf_t spi_config[] = {
166  {
167  .dev = SPI1,
168  .mosi_pin = GPIO_PIN(PORT_B, 5),
169  .miso_pin = GPIO_PIN(PORT_B, 4),
170  .sclk_pin = GPIO_PIN(PORT_B, 3),
171  .cs_pin = GPIO_UNDEF,
172  .af = GPIO_AF0,
173  .rccmask = RCC_APB2ENR_SPI1EN,
174  .apbbus = APB2
175  }
176 };
177 
178 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
179 
185 #define RTC_NUMOF (0U)
186 
192 #define ADC_NUMOF (0)
193 
195 #ifdef __cplusplus
196 }
197 #endif
198 
199 #endif /* PERIPH_CONF_H */
200 
use alternate function 7
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
use alternate function 6
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 0
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.