boards/nucleo32-f303/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLOCK_HSI (8000000U) /* external oscillator */
33 #define CLOCK_CORECLOCK (64000000U) /* desired core clock frequency */
34 
35 #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSI)
36 /* the actual PLL values are automatically generated */
37 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
38 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
39 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
40 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
41 
42 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
43 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
44 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
45 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
46 
52 static const timer_conf_t timer_config[] = {
53  {
54  .dev = TIM2,
55  .max = 0xffffffff,
56  .rcc_mask = RCC_APB1ENR_TIM2EN,
57  .bus = APB1,
58  .irqn = TIM2_IRQn
59  }
60 };
61 
62 #define TIMER_0_ISR isr_tim2
63 
64 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
65 
71 static const uart_conf_t uart_config[] = {
72  {
73  .dev = USART2,
74  .rcc_mask = RCC_APB1ENR_USART2EN,
75  .rx_pin = GPIO_PIN(PORT_A, 15),
76  .tx_pin = GPIO_PIN(PORT_A, 2),
77  .rx_af = GPIO_AF7,
78  .tx_af = GPIO_AF7,
79  .bus = APB1,
80  .irqn = USART2_IRQn
81  },
82  {
83  .dev = USART1,
84  .rcc_mask = RCC_APB2ENR_USART1EN,
85  .rx_pin = GPIO_PIN(PORT_A, 10),
86  .tx_pin = GPIO_PIN(PORT_A, 9),
87  .rx_af = GPIO_AF7,
88  .tx_af = GPIO_AF7,
89  .bus = APB2,
90  .irqn = USART1_IRQn
91  }
92 };
93 
94 #define UART_0_ISR (isr_usart2)
95 #define UART_1_ISR (isr_usart1)
96 
97 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
98 
104 static const pwm_conf_t pwm_config[] = {
105  {
106  .dev = TIM3,
107  .rcc_mask = RCC_APB1ENR_TIM3EN,
108  .chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 },
109  { .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 3 },
110  { .pin = GPIO_UNDEF, .cc_chan = 0 },
111  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
112  .af = GPIO_AF2,
113  .bus = APB1
114  },
115  {
116  .dev = TIM1,
117  .rcc_mask = RCC_APB2ENR_TIM1EN,
118  .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
119  { .pin = GPIO_UNDEF, .cc_chan = 0 },
120  { .pin = GPIO_UNDEF, .cc_chan = 0 },
121  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
122  .af = GPIO_AF6,
123  .bus = APB2
124  }
125 };
126 
127 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
128 
137 static const uint8_t spi_divtable[2][5] = {
138  { /* for APB1 @ 32000000Hz */
139  7, /* -> 125000Hz */
140  5, /* -> 500000Hz */
141  4, /* -> 1000000Hz */
142  2, /* -> 4000000Hz */
143  1 /* -> 8000000Hz */
144  },
145  { /* for APB2 @ 64000000Hz */
146  7, /* -> 250000Hz */
147  6, /* -> 500000Hz */
148  5, /* -> 1000000Hz */
149  3, /* -> 4000000Hz */
150  2 /* -> 8000000Hz */
151  }
152 };
153 
154 static const spi_conf_t spi_config[] = {
155  {
156  .dev = SPI1,
157  .mosi_pin = GPIO_PIN(PORT_B, 5),
158  .miso_pin = GPIO_PIN(PORT_B, 4),
159  .sclk_pin = GPIO_PIN(PORT_B, 3),
160  .cs_pin = GPIO_UNDEF,
161  .af = GPIO_AF0,
162  .rccmask = RCC_APB2ENR_SPI1EN,
163  .apbbus = APB2
164  }
165 };
166 
167 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
168 
174 #define RTC_NUMOF (0U)
175 
181 #define ADC_NUMOF (0)
182 
184 #ifdef __cplusplus
185 }
186 #endif
187 
188 #endif /* PERIPH_CONF_H */
189 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 6
PWM configuration structure.
use alternate function 0
LPC_CTxxBx_Type * dev
PWM device.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.