boards/nucleo32-f042/include/periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2016 OTA keys
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 48MHz */
37 #define CLOCK_CORECLOCK (48000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (0U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (0)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB2 (CLOCK_APB1)
50 
51 /* PLL factors */
52 #define CLOCK_PLL_PREDIV (2)
53 #define CLOCK_PLL_MUL (12)
54 
61 static const timer_conf_t timer_config[] = {
62  {
63  .dev = TIM2,
64  .max = 0xffffffff,
65  .rcc_mask = RCC_APB1ENR_TIM2EN,
66  .bus = APB1,
67  .irqn = TIM2_IRQn
68  }
69 };
70 
71 #define TIMER_0_ISR isr_tim2
72 
73 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
74 
80 static const uart_conf_t uart_config[] = {
81  {
82  .dev = USART2,
83  .rcc_mask = RCC_APB1ENR_USART2EN,
84  .rx_pin = GPIO_PIN(PORT_A, 15),
85  .tx_pin = GPIO_PIN(PORT_A, 2),
86  .rx_af = GPIO_AF1,
87  .tx_af = GPIO_AF1,
88  .bus = APB1,
89  .irqn = USART2_IRQn
90  },
91  {
92  .dev = USART1,
93  .rcc_mask = RCC_APB2ENR_USART1EN,
94  .rx_pin = GPIO_PIN(PORT_A, 10),
95  .tx_pin = GPIO_PIN(PORT_A, 9),
96  .rx_af = GPIO_AF1,
97  .tx_af = GPIO_AF1,
98  .bus = APB2,
99  .irqn = USART1_IRQn
100  }
101 };
102 
103 #define UART_0_ISR (isr_usart2)
104 #define UART_1_ISR (isr_usart1)
105 
106 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
107 
113 static const pwm_conf_t pwm_config[] = {
114  {
115  .dev = TIM1,
116  .rcc_mask = RCC_APB2ENR_TIM1EN,
117  .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
118  { .pin = GPIO_UNDEF, .cc_chan = 0 },
119  { .pin = GPIO_UNDEF, .cc_chan = 0 },
120  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
121  .af = GPIO_AF2,
122  .bus = APB2
123  },
124  {
125  .dev = TIM14,
126  .rcc_mask = RCC_APB1ENR_TIM14EN,
127  .chan = { { .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 0 },
128  { .pin = GPIO_UNDEF, .cc_chan = 0 },
129  { .pin = GPIO_UNDEF, .cc_chan = 0 },
130  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
131  .af = GPIO_AF0,
132  .bus = APB1
133  },
134  {
135  .dev = TIM3,
136  .rcc_mask = RCC_APB1ENR_TIM3EN,
137  .chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 },
138  { .pin = GPIO_UNDEF, .cc_chan = 0 },
139  { .pin = GPIO_UNDEF, .cc_chan = 0 },
140  { .pin = GPIO_UNDEF, .cc_chan = 0 }},
141  .af = GPIO_AF1,
142  .bus = APB1
143  }
144 };
145 
146 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
147 
156 static const uint8_t spi_divtable[2][5] = {
157  { /* for APB1 @ 48000000Hz */
158  7, /* -> 187500Hz */
159  6, /* -> 375000Hz */
160  5, /* -> 750000Hz */
161  2, /* -> 6000000Hz */
162  1 /* -> 12000000Hz */
163  },
164  { /* for APB2 @ 48000000Hz */
165  7, /* -> 187500Hz */
166  6, /* -> 375000Hz */
167  5, /* -> 750000Hz */
168  2, /* -> 6000000Hz */
169  1 /* -> 12000000Hz */
170  }
171 };
172 
173 static const spi_conf_t spi_config[] = {
174  {
175  .dev = SPI1,
176  .mosi_pin = GPIO_PIN(PORT_B, 5),
177  .miso_pin = GPIO_PIN(PORT_B, 4),
178  .sclk_pin = GPIO_PIN(PORT_B, 3),
179  .cs_pin = GPIO_UNDEF,
180  .af = GPIO_AF0,
181  .rccmask = RCC_APB2ENR_SPI1EN,
182  .apbbus = APB2
183  }
184 };
185 
186 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
187 
197 #define RTC_NUMOF (0U)
198 
204 #define ADC_CONFIG { \
205  { GPIO_PIN(PORT_A, 0), 0 }, \
206  { GPIO_PIN(PORT_A, 1), 1 }, \
207  { GPIO_PIN(PORT_A, 3), 3 }, \
208  { GPIO_PIN(PORT_A, 4), 4 }, \
209  { GPIO_PIN(PORT_A, 7), 7 } \
210 }
211 
212 #define ADC_NUMOF (5)
213 
215 #ifdef __cplusplus
216 }
217 #endif
218 
219 #endif /* PERIPH_CONF_H */
220 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
NRF_TIMER_Type * dev
timer device
use alternate function 0
Tcc * dev
TCC device to use.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.