boards/nucleo32-f031/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * 2017 OTA keys
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 #define CLOCK_HSI (8000000U) /* internal oscillator */
34 #define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */
35 
36 /* the actual PLL values are automatically generated */
37 #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSI)
38 
39 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
40 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
41 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
42 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
43 
49 static const timer_conf_t timer_config[] = {
50  {
51  .dev = TIM2,
52  .max = 0xffffffff,
53  .rcc_mask = RCC_APB1ENR_TIM2EN,
54  .bus = APB1,
55  .irqn = TIM2_IRQn
56  }
57 };
58 
59 #define TIMER_0_ISR isr_tim2
60 
61 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
62 
68 static const uart_conf_t uart_config[] = {
69  {
70  .dev = USART1,
71  .rcc_mask = RCC_APB2ENR_USART1EN,
72  .rx_pin = GPIO_PIN(PORT_A, 15),
73  .tx_pin = GPIO_PIN(PORT_A, 2),
74  .rx_af = GPIO_AF1,
75  .tx_af = GPIO_AF1,
76  .bus = APB2,
77  .irqn = USART1_IRQn
78  }
79 };
80 
81 #define UART_0_ISR (isr_usart1)
82 
83 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
84 
90 static const pwm_conf_t pwm_config[] = {
91  {
92  .dev = TIM1,
93  .rcc_mask = RCC_APB2ENR_TIM1EN,
94  .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
95  { .pin = GPIO_UNDEF, .cc_chan = 0 },
96  { .pin = GPIO_UNDEF, .cc_chan = 0 },
97  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
98  .af = GPIO_AF2,
99  .bus = APB2
100  },
101  {
102  .dev = TIM14,
103  .rcc_mask = RCC_APB1ENR_TIM14EN,
104  .chan = { { .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 0 },
105  { .pin = GPIO_UNDEF, .cc_chan = 0 },
106  { .pin = GPIO_UNDEF, .cc_chan = 0 },
107  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
108  .af = GPIO_AF0,
109  .bus = APB1
110  },
111  {
112  .dev = TIM3,
113  .rcc_mask = RCC_APB1ENR_TIM3EN,
114  .chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 },
115  { .pin = GPIO_UNDEF, .cc_chan = 0 },
116  { .pin = GPIO_UNDEF, .cc_chan = 0 },
117  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
118  .af = GPIO_AF1,
119  .bus = APB1
120  },
121 };
122 
123 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
124 
133 static const uint8_t spi_divtable[2][5] = {
134  { /* for APB1 @ 48000000Hz */
135  7, /* -> 187500Hz */
136  6, /* -> 375000Hz */
137  5, /* -> 750000Hz */
138  2, /* -> 6000000Hz */
139  1 /* -> 12000000Hz */
140  },
141  { /* for APB2 @ 48000000Hz */
142  7, /* -> 187500Hz */
143  6, /* -> 375000Hz */
144  5, /* -> 750000Hz */
145  2, /* -> 6000000Hz */
146  1 /* -> 12000000Hz */
147  }
148 };
149 
150 static const spi_conf_t spi_config[] = {
151  {
152  .dev = SPI1,
153  .mosi_pin = GPIO_PIN(PORT_B, 5),
154  .miso_pin = GPIO_PIN(PORT_B, 4),
155  .sclk_pin = GPIO_PIN(PORT_B, 3),
156  .cs_pin = GPIO_UNDEF,
157  .af = GPIO_AF0,
158  .rccmask = RCC_APB2ENR_SPI1EN,
159  .apbbus = APB2
160  }
161 };
162 
163 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
164 
174 #define RTC_NUMOF (0U)
175 
181 #define ADC_CONFIG { \
182  { GPIO_PIN(PORT_A, 0), 0 }, \
183  { GPIO_PIN(PORT_A, 1), 1 }, \
184  { GPIO_PIN(PORT_A, 3), 3 }, \
185  { GPIO_PIN(PORT_A, 4), 4 }, \
186  { GPIO_PIN(PORT_A, 7), 7 } \
187 }
188 
189 #define ADC_NUMOF (5)
190 
196 #define DAC_NUMOF (0)
197 
199 #ifdef __cplusplus
200 }
201 #endif
202 
203 #endif /* PERIPH_CONF_H */
204 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
use alternate function 0
LPC_CTxxBx_Type * dev
PWM device.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.