boards/nucleo32-f031/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * 2017 OTA keys
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
36 /* give the target core clock (HCLK) frequency [in Hz],
37  * maximum: 48MHz */
38 #define CLOCK_CORECLOCK (48000000U)
39 /* 0: no external high speed crystal available
40  * else: actual crystal frequency [in Hz] */
41 #define CLOCK_HSE (0U)
42 /* 0: no external low speed crystal available,
43  * 1: external crystal available (always 32.768kHz) */
44 #define CLOCK_LSE (0)
45 /* peripheral clock setup */
46 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
47 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
48 #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
49 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
50 #define CLOCK_APB2 (CLOCK_APB1)
51 
52 /* PLL factors */
53 #define CLOCK_PLL_PREDIV (2)
54 #define CLOCK_PLL_MUL (12)
55 
61 static const timer_conf_t timer_config[] = {
62  {
63  .dev = TIM2,
64  .max = 0xffffffff,
65  .rcc_mask = RCC_APB1ENR_TIM2EN,
66  .bus = APB1,
67  .irqn = TIM2_IRQn
68  }
69 };
70 
71 #define TIMER_0_ISR isr_tim2
72 
73 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
74 
80 static const uart_conf_t uart_config[] = {
81  {
82  .dev = USART1,
83  .rcc_mask = RCC_APB2ENR_USART1EN,
84  .rx_pin = GPIO_PIN(PORT_A, 15),
85  .tx_pin = GPIO_PIN(PORT_A, 2),
86  .rx_af = GPIO_AF1,
87  .tx_af = GPIO_AF1,
88  .bus = APB2,
89  .irqn = USART1_IRQn
90  }
91 };
92 
93 #define UART_0_ISR (isr_usart1)
94 
95 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
96 
102 static const pwm_conf_t pwm_config[] = {
103  {
104  .dev = TIM1,
105  .rcc_mask = RCC_APB2ENR_TIM1EN,
106  .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
107  { .pin = GPIO_UNDEF, .cc_chan = 0 },
108  { .pin = GPIO_UNDEF, .cc_chan = 0 },
109  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
110  .af = GPIO_AF2,
111  .bus = APB2
112  },
113  {
114  .dev = TIM14,
115  .rcc_mask = RCC_APB1ENR_TIM14EN,
116  .chan = { { .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 0 },
117  { .pin = GPIO_UNDEF, .cc_chan = 0 },
118  { .pin = GPIO_UNDEF, .cc_chan = 0 },
119  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
120  .af = GPIO_AF0,
121  .bus = APB1
122  },
123  {
124  .dev = TIM3,
125  .rcc_mask = RCC_APB1ENR_TIM3EN,
126  .chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 },
127  { .pin = GPIO_UNDEF, .cc_chan = 0 },
128  { .pin = GPIO_UNDEF, .cc_chan = 0 },
129  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
130  .af = GPIO_AF1,
131  .bus = APB1
132  },
133 };
134 
135 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
136 
145 static const uint8_t spi_divtable[2][5] = {
146  { /* for APB1 @ 48000000Hz */
147  7, /* -> 187500Hz */
148  6, /* -> 375000Hz */
149  5, /* -> 750000Hz */
150  2, /* -> 6000000Hz */
151  1 /* -> 12000000Hz */
152  },
153  { /* for APB2 @ 48000000Hz */
154  7, /* -> 187500Hz */
155  6, /* -> 375000Hz */
156  5, /* -> 750000Hz */
157  2, /* -> 6000000Hz */
158  1 /* -> 12000000Hz */
159  }
160 };
161 
162 static const spi_conf_t spi_config[] = {
163  {
164  .dev = SPI1,
165  .mosi_pin = GPIO_PIN(PORT_B, 5),
166  .miso_pin = GPIO_PIN(PORT_B, 4),
167  .sclk_pin = GPIO_PIN(PORT_B, 3),
168  .cs_pin = GPIO_UNDEF,
169  .af = GPIO_AF0,
170  .rccmask = RCC_APB2ENR_SPI1EN,
171  .apbbus = APB2
172  }
173 };
174 
175 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
176 
186 #define RTC_NUMOF (0U)
187 
193 #define ADC_CONFIG { \
194  { GPIO_PIN(PORT_A, 0), 0 }, \
195  { GPIO_PIN(PORT_A, 1), 1 }, \
196  { GPIO_PIN(PORT_A, 3), 3 }, \
197  { GPIO_PIN(PORT_A, 4), 4 }, \
198  { GPIO_PIN(PORT_A, 7), 7 } \
199 }
200 
201 #define ADC_NUMOF (5)
202 
204 #ifdef __cplusplus
205 }
206 #endif
207 
208 #endif /* PERIPH_CONF_H */
209 
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
NRF_TIMER_Type * dev
timer device
use alternate function 0
Tcc * dev
TCC device to use.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.