boards/nucleo32-f031/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  * 2017 OTA keys
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
22 #ifndef PERIPH_CONF_H
23 #define PERIPH_CONF_H
24 
25 #include "periph_cpu.h"
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif
30 
38 /* give the target core clock (HCLK) frequency [in Hz],
39  * maximum: 48MHz */
40 #define CLOCK_CORECLOCK (48000000U)
41 /* 0: no external high speed crystal available
42  * else: actual crystal frequency [in Hz] */
43 #define CLOCK_HSE (0U)
44 /* 0: no external low speed crystal available,
45  * 1: external crystal available (always 32.768kHz) */
46 #define CLOCK_LSE (0)
47 /* peripheral clock setup */
48 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
49 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
50 #define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
51 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
52 #define CLOCK_APB2 (CLOCK_APB1)
53 
54 /* PLL factors */
55 #define CLOCK_PLL_PREDIV (2)
56 #define CLOCK_PLL_MUL (12)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM2,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM2EN,
68  .bus = APB1,
69  .irqn = TIM2_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim2
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART1,
85  .rcc_mask = RCC_APB2ENR_USART1EN,
86  .rx_pin = GPIO_PIN(PORT_A, 15),
87  .tx_pin = GPIO_PIN(PORT_A, 2),
88  .rx_af = GPIO_AF1,
89  .tx_af = GPIO_AF1,
90  .bus = APB2,
91  .irqn = USART1_IRQn
92  }
93 };
94 
95 #define UART_0_ISR (isr_usart1)
96 
97 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
98 
104 static const pwm_conf_t pwm_config[] = {
105  {
106  .dev = TIM1,
107  .rcc_mask = RCC_APB2ENR_TIM1EN,
108  .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
109  { .pin = GPIO_UNDEF, .cc_chan = 0 },
110  { .pin = GPIO_UNDEF, .cc_chan = 0 },
111  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
112  .af = GPIO_AF2,
113  .bus = APB2
114  },
115  {
116  .dev = TIM14,
117  .rcc_mask = RCC_APB1ENR_TIM14EN,
118  .chan = { { .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 0 },
119  { .pin = GPIO_UNDEF, .cc_chan = 0 },
120  { .pin = GPIO_UNDEF, .cc_chan = 0 },
121  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
122  .af = GPIO_AF0,
123  .bus = APB1
124  },
125  {
126  .dev = TIM3,
127  .rcc_mask = RCC_APB1ENR_TIM3EN,
128  .chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 },
129  { .pin = GPIO_UNDEF, .cc_chan = 0 },
130  { .pin = GPIO_UNDEF, .cc_chan = 0 },
131  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
132  .af = GPIO_AF1,
133  .bus = APB1
134  },
135 };
136 
137 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
138 
147 static const uint8_t spi_divtable[2][5] = {
148  { /* for APB1 @ 48000000Hz */
149  7, /* -> 187500Hz */
150  6, /* -> 375000Hz */
151  5, /* -> 750000Hz */
152  2, /* -> 6000000Hz */
153  1 /* -> 12000000Hz */
154  },
155  { /* for APB2 @ 48000000Hz */
156  7, /* -> 187500Hz */
157  6, /* -> 375000Hz */
158  5, /* -> 750000Hz */
159  2, /* -> 6000000Hz */
160  1 /* -> 12000000Hz */
161  }
162 };
163 
164 static const spi_conf_t spi_config[] = {
165  {
166  .dev = SPI1,
167  .mosi_pin = GPIO_PIN(PORT_B, 5),
168  .miso_pin = GPIO_PIN(PORT_B, 4),
169  .sclk_pin = GPIO_PIN(PORT_B, 3),
170  .cs_pin = GPIO_UNDEF,
171  .af = GPIO_AF0,
172  .rccmask = RCC_APB2ENR_SPI1EN,
173  .apbbus = APB2
174  }
175 };
176 
177 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
178 
188 #define RTC_NUMOF (0U)
189 
195 #define ADC_CONFIG { \
196  { GPIO_PIN(PORT_A, 0), 0 }, \
197  { GPIO_PIN(PORT_A, 1), 1 }, \
198  { GPIO_PIN(PORT_A, 3), 3 }, \
199  { GPIO_PIN(PORT_A, 4), 4 }, \
200  { GPIO_PIN(PORT_A, 7), 7 } \
201 }
202 
203 #define ADC_NUMOF (5)
204 
206 #ifdef __cplusplus
207 }
208 #endif
209 
210 #endif /* PERIPH_CONF_H */
211 
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 0
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.