boards/nucleo144-f446/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 180MHz */
39 #define CLOCK_CORECLOCK (180000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (8000000U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (1)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
53 
54 /* Main PLL factors */
55 #define CLOCK_PLL_M (4)
56 #define CLOCK_PLL_N (180)
57 #define CLOCK_PLL_P (2)
58 #define CLOCK_PLL_Q (0)
59 
60 /* PLL SAI configuration */
61 #define CLOCK_ENABLE_PLL_SAI (1)
62 #define CLOCK_PLL_SAI_M (4)
63 #define CLOCK_PLL_SAI_N (192)
64 #define CLOCK_PLL_SAI_P (8)
65 #define CLOCK_PLL_SAI_Q (0)
66 
67 /* Use alternative source for 48MHz clock */
68 #define CLOCK_USE_ALT_48MHZ (1)
69 
75 static const timer_conf_t timer_config[] = {
76  {
77  .dev = TIM5,
78  .max = 0xffffffff,
79  .rcc_mask = RCC_APB1ENR_TIM5EN,
80  .bus = APB1,
81  .irqn = TIM5_IRQn
82  }
83 };
84 
85 #define TIMER_0_ISR isr_tim5
86 
87 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
88 
94 static const uart_conf_t uart_config[] = {
95  {
96  .dev = USART3,
97  .rcc_mask = RCC_APB1ENR_USART3EN,
98  .rx_pin = GPIO_PIN(PORT_D, 9),
99  .tx_pin = GPIO_PIN(PORT_D, 8),
100  .rx_af = GPIO_AF7,
101  .tx_af = GPIO_AF7,
102  .bus = APB1,
103  .irqn = USART3_IRQn,
104 #ifdef UART_USE_DMA
105  .dma_stream = 6,
106  .dma_chan = 4
107 #endif
108  },
109  {
110  .dev = USART6,
111  .rcc_mask = RCC_APB2ENR_USART6EN,
112  .rx_pin = GPIO_PIN(PORT_G, 9),
113  .tx_pin = GPIO_PIN(PORT_G, 14),
114  .rx_af = GPIO_AF8,
115  .tx_af = GPIO_AF8,
116  .bus = APB2,
117  .irqn = USART6_IRQn,
118 #ifdef UART_USE_DMA
119  .dma_stream = 5,
120  .dma_chan = 4
121 #endif
122  },
123  {
124  .dev = USART2,
125  .rcc_mask = RCC_APB1ENR_USART2EN,
126  .rx_pin = GPIO_PIN(PORT_D, 6),
127  .tx_pin = GPIO_PIN(PORT_D, 5),
128  .rx_af = GPIO_AF7,
129  .tx_af = GPIO_AF7,
130  .bus = APB1,
131  .irqn = USART2_IRQn,
132 #ifdef UART_USE_DMA
133  .dma_stream = 4,
134  .dma_chan = 4
135 #endif
136  },
137 };
138 
139 #define UART_0_ISR (isr_usart3)
140 #define UART_0_DMA_ISR (isr_dma1_stream6)
141 #define UART_1_ISR (isr_usart6)
142 #define UART_1_DMA_ISR (isr_dma1_stream5)
143 #define UART_2_ISR (isr_usart2)
144 #define UART_2_DMA_ISR (isr_dma1_stream4)
145 
146 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
147 
153 static const pwm_conf_t pwm_config[] = {
154  {
155  .dev = TIM1,
156  .rcc_mask = RCC_APB2ENR_TIM1EN,
157  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
158  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
159  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
160  { .pin = GPIO_UNDEF, .cc_chan = 0} },
161  .af = GPIO_AF1,
162  .bus = APB2
163  },
164  {
165  .dev = TIM4,
166  .rcc_mask = RCC_APB1ENR_TIM4EN,
167  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
168  { .pin = GPIO_UNDEF, .cc_chan = 0},
169  { .pin = GPIO_UNDEF, .cc_chan = 0},
170  { .pin = GPIO_UNDEF, .cc_chan = 0} },
171  .af = GPIO_AF2,
172  .bus = APB1
173  },
174 };
175 
176 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
177 
186 static const uint8_t spi_divtable[2][5] = {
187  { /* for APB1 @ 90000000Hz */
188  7, /* -> 351562Hz */
189  7, /* -> 351562Hz */
190  6, /* -> 703125Hz */
191  3, /* -> 5625000Hz */
192  2 /* -> 11250000Hz */
193  },
194  { /* for APB2 @ 180000000Hz */
195  7, /* -> 703125Hz */
196  7, /* -> 703125Hz */
197  7, /* -> 703125Hz */
198  4, /* -> 5625000Hz */
199  3 /* -> 11250000Hz */
200  }
201 };
202 
203 static const spi_conf_t spi_config[] = {
204  {
205  .dev = SPI1,
206  .mosi_pin = GPIO_PIN(PORT_A, 7),
207  .miso_pin = GPIO_PIN(PORT_A, 6),
208  .sclk_pin = GPIO_PIN(PORT_A, 5),
209  .cs_pin = GPIO_UNDEF,
210  .af = GPIO_AF5,
211  .rccmask = RCC_APB2ENR_SPI1EN,
212  .apbbus = APB2
213  }
214 };
215 
216 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
217 
223 #define I2C_NUMOF (1U)
224 #define I2C_0_EN 1
225 #define I2C_IRQ_PRIO 1
226 #define I2C_APBCLK (42000000U)
227 
228 /* I2C 0 device configuration */
229 #define I2C_0_DEV I2C1
230 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
231 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
232 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
233 #define I2C_0_EVT_ISR isr_i2c1_ev
234 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
235 #define I2C_0_ERR_ISR isr_i2c1_er
236 /* I2C 0 pin configuration */
237 #define I2C_0_SCL_PORT GPIOB
238 #define I2C_0_SCL_PIN 8
239 #define I2C_0_SCL_AF 4
240 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
241 #define I2C_0_SDA_PORT GPIOB
242 #define I2C_0_SDA_PIN 9
243 #define I2C_0_SDA_AF 4
244 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
245 
251 #define ADC_NUMOF (0)
252 
254 #ifdef __cplusplus
255 }
256 #endif
257 
258 #endif /* PERIPH_CONF_H */
259 
use alternate function 7
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
use alternate function 8
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.