boards/nucleo144-f446/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 180MHz */
37 #define CLOCK_CORECLOCK (180000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (8000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (1)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
49 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
51 
52 /* Main PLL factors */
53 #define CLOCK_PLL_M (4)
54 #define CLOCK_PLL_N (180)
55 #define CLOCK_PLL_P (2)
56 #define CLOCK_PLL_Q (0)
57 
58 /* PLL SAI configuration */
59 #define CLOCK_ENABLE_PLL_SAI (1)
60 #define CLOCK_PLL_SAI_M (4)
61 #define CLOCK_PLL_SAI_N (192)
62 #define CLOCK_PLL_SAI_P (8)
63 #define CLOCK_PLL_SAI_Q (0)
64 
65 /* Use alternative source for 48MHz clock */
66 #define CLOCK_USE_ALT_48MHZ (1)
67 
73 static const timer_conf_t timer_config[] = {
74  {
75  .dev = TIM5,
76  .max = 0xffffffff,
77  .rcc_mask = RCC_APB1ENR_TIM5EN,
78  .bus = APB1,
79  .irqn = TIM5_IRQn
80  }
81 };
82 
83 #define TIMER_0_ISR isr_tim5
84 
85 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
86 
92 static const uart_conf_t uart_config[] = {
93  {
94  .dev = USART3,
95  .rcc_mask = RCC_APB1ENR_USART3EN,
96  .rx_pin = GPIO_PIN(PORT_D, 9),
97  .tx_pin = GPIO_PIN(PORT_D, 8),
98  .rx_af = GPIO_AF7,
99  .tx_af = GPIO_AF7,
100  .bus = APB1,
101  .irqn = USART3_IRQn,
102 #ifdef UART_USE_DMA
103  .dma_stream = 6,
104  .dma_chan = 4
105 #endif
106  },
107  {
108  .dev = USART6,
109  .rcc_mask = RCC_APB2ENR_USART6EN,
110  .rx_pin = GPIO_PIN(PORT_G, 9),
111  .tx_pin = GPIO_PIN(PORT_G, 14),
112  .rx_af = GPIO_AF8,
113  .tx_af = GPIO_AF8,
114  .bus = APB2,
115  .irqn = USART6_IRQn,
116 #ifdef UART_USE_DMA
117  .dma_stream = 5,
118  .dma_chan = 4
119 #endif
120  },
121  {
122  .dev = USART2,
123  .rcc_mask = RCC_APB1ENR_USART2EN,
124  .rx_pin = GPIO_PIN(PORT_D, 6),
125  .tx_pin = GPIO_PIN(PORT_D, 5),
126  .rx_af = GPIO_AF7,
127  .tx_af = GPIO_AF7,
128  .bus = APB1,
129  .irqn = USART2_IRQn,
130 #ifdef UART_USE_DMA
131  .dma_stream = 4,
132  .dma_chan = 4
133 #endif
134  },
135 };
136 
137 #define UART_0_ISR (isr_usart3)
138 #define UART_0_DMA_ISR (isr_dma1_stream6)
139 #define UART_1_ISR (isr_usart6)
140 #define UART_1_DMA_ISR (isr_dma1_stream5)
141 #define UART_2_ISR (isr_usart2)
142 #define UART_2_DMA_ISR (isr_dma1_stream4)
143 
144 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
145 
151 static const pwm_conf_t pwm_config[] = {
152  {
153  .dev = TIM1,
154  .rcc_mask = RCC_APB2ENR_TIM1EN,
155  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
156  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
157  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
158  { .pin = GPIO_UNDEF, .cc_chan = 0} },
159  .af = GPIO_AF1,
160  .bus = APB2
161  },
162  {
163  .dev = TIM4,
164  .rcc_mask = RCC_APB1ENR_TIM4EN,
165  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
166  { .pin = GPIO_UNDEF, .cc_chan = 0},
167  { .pin = GPIO_UNDEF, .cc_chan = 0},
168  { .pin = GPIO_UNDEF, .cc_chan = 0} },
169  .af = GPIO_AF2,
170  .bus = APB1
171  },
172 };
173 
174 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
175 
184 static const uint8_t spi_divtable[2][5] = {
185  { /* for APB1 @ 90000000Hz */
186  7, /* -> 351562Hz */
187  7, /* -> 351562Hz */
188  6, /* -> 703125Hz */
189  3, /* -> 5625000Hz */
190  2 /* -> 11250000Hz */
191  },
192  { /* for APB2 @ 180000000Hz */
193  7, /* -> 703125Hz */
194  7, /* -> 703125Hz */
195  7, /* -> 703125Hz */
196  4, /* -> 5625000Hz */
197  3 /* -> 11250000Hz */
198  }
199 };
200 
201 static const spi_conf_t spi_config[] = {
202  {
203  .dev = SPI1,
204  .mosi_pin = GPIO_PIN(PORT_A, 7),
205  .miso_pin = GPIO_PIN(PORT_A, 6),
206  .sclk_pin = GPIO_PIN(PORT_A, 5),
207  .cs_pin = GPIO_UNDEF,
208  .af = GPIO_AF5,
209  .rccmask = RCC_APB2ENR_SPI1EN,
210  .apbbus = APB2
211  }
212 };
213 
214 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
215 
221 #define I2C_NUMOF (1U)
222 #define I2C_0_EN 1
223 #define I2C_IRQ_PRIO 1
224 #define I2C_APBCLK (42000000U)
225 
226 /* I2C 0 device configuration */
227 #define I2C_0_DEV I2C1
228 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
229 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
230 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
231 #define I2C_0_EVT_ISR isr_i2c1_ev
232 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
233 #define I2C_0_ERR_ISR isr_i2c1_er
234 /* I2C 0 pin configuration */
235 #define I2C_0_SCL_PORT GPIOB
236 #define I2C_0_SCL_PIN 8
237 #define I2C_0_SCL_AF 4
238 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
239 #define I2C_0_SDA_PORT GPIOB
240 #define I2C_0_SDA_PIN 9
241 #define I2C_0_SDA_AF 4
242 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
243 
249 #define ADC_NUMOF (0)
250 
252 #ifdef __cplusplus
253 }
254 #endif
255 
256 #endif /* PERIPH_CONF_H */
257 
use alternate function 7
USART_TypeDef * dev
USART device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
NRF_TIMER_Type * dev
timer device
use alternate function 5
Tcc * dev
TCC device to use.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.