boards/nucleo144-f429/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLOCK_HSE (8000000U) /* external oscillator */
33 #define CLOCK_CORECLOCK (180000000U) /* desired core clock frequency */
34 
35 /* the actual PLL values are automatically generated */
36 #define CLOCK_PLL_M (CLOCK_HSE / 1000000)
37 #define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
38 #define CLOCK_PLL_P (2U)
39 #define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
40 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
41 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
42 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
43 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
44 
45 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
48 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
49 
55 static const timer_conf_t timer_config[] = {
56  {
57  .dev = TIM5,
58  .max = 0xffffffff,
59  .rcc_mask = RCC_APB1ENR_TIM5EN,
60  .bus = APB1,
61  .irqn = TIM5_IRQn
62  }
63 };
64 
65 #define TIMER_0_ISR isr_tim5
66 
67 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
68 
74 static const uart_conf_t uart_config[] = {
75  {
76  .dev = USART3,
77  .rcc_mask = RCC_APB1ENR_USART3EN,
78  .rx_pin = GPIO_PIN(PORT_D, 9),
79  .tx_pin = GPIO_PIN(PORT_D, 8),
80  .rx_af = GPIO_AF7,
81  .tx_af = GPIO_AF7,
82  .bus = APB1,
83  .irqn = USART3_IRQn,
84 #ifdef UART_USE_DMA
85  .dma_stream = 6,
86  .dma_chan = 4
87 #endif
88  },
89  {
90  .dev = USART6,
91  .rcc_mask = RCC_APB2ENR_USART6EN,
92  .rx_pin = GPIO_PIN(PORT_G, 9),
93  .tx_pin = GPIO_PIN(PORT_G, 14),
94  .rx_af = GPIO_AF8,
95  .tx_af = GPIO_AF8,
96  .bus = APB2,
97  .irqn = USART6_IRQn,
98 #ifdef UART_USE_DMA
99  .dma_stream = 5,
100  .dma_chan = 4
101 #endif
102  },
103  {
104  .dev = USART2,
105  .rcc_mask = RCC_APB1ENR_USART2EN,
106  .rx_pin = GPIO_PIN(PORT_D, 6),
107  .tx_pin = GPIO_PIN(PORT_D, 5),
108  .rx_af = GPIO_AF7,
109  .tx_af = GPIO_AF7,
110  .bus = APB1,
111  .irqn = USART2_IRQn,
112 #ifdef UART_USE_DMA
113  .dma_stream = 4,
114  .dma_chan = 4
115 #endif
116  },
117 };
118 
119 #define UART_0_ISR (isr_usart3)
120 #define UART_0_DMA_ISR (isr_dma1_stream6)
121 #define UART_1_ISR (isr_usart6)
122 #define UART_1_DMA_ISR (isr_dma1_stream5)
123 #define UART_2_ISR (isr_usart2)
124 #define UART_2_DMA_ISR (isr_dma1_stream4)
125 
126 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
127 
133 static const pwm_conf_t pwm_config[] = {
134  {
135  .dev = TIM1,
136  .rcc_mask = RCC_APB2ENR_TIM1EN,
137  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
138  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
139  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
140  { .pin = GPIO_UNDEF, .cc_chan = 0} },
141  .af = GPIO_AF1,
142  .bus = APB2
143  },
144  {
145  .dev = TIM4,
146  .rcc_mask = RCC_APB1ENR_TIM4EN,
147  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
148  { .pin = GPIO_UNDEF, .cc_chan = 0},
149  { .pin = GPIO_UNDEF, .cc_chan = 0},
150  { .pin = GPIO_UNDEF, .cc_chan = 0} },
151  .af = GPIO_AF2,
152  .bus = APB1
153  },
154 };
155 
156 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
157 
166 static const uint8_t spi_divtable[2][5] = {
167  { /* for APB1 @ 90000000Hz */
168  7, /* -> 351562Hz */
169  7, /* -> 351562Hz */
170  6, /* -> 703125Hz */
171  3, /* -> 5625000Hz */
172  2 /* -> 11250000Hz */
173  },
174  { /* for APB2 @ 180000000Hz */
175  7, /* -> 703125Hz */
176  7, /* -> 703125Hz */
177  7, /* -> 703125Hz */
178  4, /* -> 5625000Hz */
179  3 /* -> 11250000Hz */
180  }
181 };
182 
183 static const spi_conf_t spi_config[] = {
184  {
185  .dev = SPI1,
186  .mosi_pin = GPIO_PIN(PORT_A, 7),
187  .miso_pin = GPIO_PIN(PORT_A, 6),
188  .sclk_pin = GPIO_PIN(PORT_A, 5),
189  .cs_pin = GPIO_UNDEF,
190  .af = GPIO_AF5,
191  .rccmask = RCC_APB2ENR_SPI1EN,
192  .apbbus = APB2
193  }
194 };
195 
196 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
197 
203 #define I2C_NUMOF (1U)
204 #define I2C_0_EN 1
205 #define I2C_IRQ_PRIO 1
206 #define I2C_APBCLK (42000000U)
207 
208 /* I2C 0 device configuration */
209 #define I2C_0_DEV I2C1
210 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
211 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
212 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
213 #define I2C_0_EVT_ISR isr_i2c1_ev
214 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
215 #define I2C_0_ERR_ISR isr_i2c1_er
216 /* I2C 0 pin configuration */
217 #define I2C_0_SCL_PORT GPIOB
218 #define I2C_0_SCL_PIN 8
219 #define I2C_0_SCL_AF 4
220 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
221 #define I2C_0_SDA_PORT GPIOB
222 #define I2C_0_SDA_PIN 9
223 #define I2C_0_SDA_AF 4
224 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
225 
231 #define ADC_NUMOF (0)
232 
238 #define DAC_NUMOF (0)
239 
241 #ifdef __cplusplus
242 }
243 #endif
244 
245 #endif /* PERIPH_CONF_H */
246 
use alternate function 7
USART_TypeDef * dev
USART device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.