boards/nucleo144-f429/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* 0: no external high speed crystal available
33  * else: actual crystal frequency [in Hz] */
34 #define CLOCK_HSE (8000000U)
35 /* 0: no external low speed crystal available,
36  * 1: external crystal available (always 32.768kHz) */
37 #define CLOCK_LSE (1)
38 /* give the target core clock (HCLK) frequency [in Hz],
39  * maximum: 180MHz */
40 #define CLOCK_CORECLOCK (168000000U)
41 /* peripheral clock setup */
42 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
43 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
44 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
45 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
46 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
47 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
48 
54 static const timer_conf_t timer_config[] = {
55  {
56  .dev = TIM5,
57  .max = 0xffffffff,
58  .rcc_mask = RCC_APB1ENR_TIM5EN,
59  .bus = APB1,
60  .irqn = TIM5_IRQn
61  }
62 };
63 
64 #define TIMER_0_ISR isr_tim5
65 
66 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
67 
73 static const uart_conf_t uart_config[] = {
74  {
75  .dev = USART3,
76  .rcc_mask = RCC_APB1ENR_USART3EN,
77  .rx_pin = GPIO_PIN(PORT_D, 9),
78  .tx_pin = GPIO_PIN(PORT_D, 8),
79  .rx_af = GPIO_AF7,
80  .tx_af = GPIO_AF7,
81  .bus = APB1,
82  .irqn = USART3_IRQn,
83 #ifdef UART_USE_DMA
84  .dma_stream = 6,
85  .dma_chan = 4
86 #endif
87  },
88  {
89  .dev = USART6,
90  .rcc_mask = RCC_APB2ENR_USART6EN,
91  .rx_pin = GPIO_PIN(PORT_G, 9),
92  .tx_pin = GPIO_PIN(PORT_G, 14),
93  .rx_af = GPIO_AF8,
94  .tx_af = GPIO_AF8,
95  .bus = APB2,
96  .irqn = USART6_IRQn,
97 #ifdef UART_USE_DMA
98  .dma_stream = 5,
99  .dma_chan = 4
100 #endif
101  },
102  {
103  .dev = USART2,
104  .rcc_mask = RCC_APB1ENR_USART2EN,
105  .rx_pin = GPIO_PIN(PORT_D, 6),
106  .tx_pin = GPIO_PIN(PORT_D, 5),
107  .rx_af = GPIO_AF7,
108  .tx_af = GPIO_AF7,
109  .bus = APB1,
110  .irqn = USART2_IRQn,
111 #ifdef UART_USE_DMA
112  .dma_stream = 4,
113  .dma_chan = 4
114 #endif
115  },
116 };
117 
118 #define UART_0_ISR (isr_usart3)
119 #define UART_0_DMA_ISR (isr_dma1_stream6)
120 #define UART_1_ISR (isr_usart6)
121 #define UART_1_DMA_ISR (isr_dma1_stream5)
122 #define UART_2_ISR (isr_usart2)
123 #define UART_2_DMA_ISR (isr_dma1_stream4)
124 
125 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
126 
132 static const pwm_conf_t pwm_config[] = {
133  {
134  .dev = TIM1,
135  .rcc_mask = RCC_APB2ENR_TIM1EN,
136  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
137  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
138  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
139  { .pin = GPIO_UNDEF, .cc_chan = 0} },
140  .af = GPIO_AF1,
141  .bus = APB2
142  },
143  {
144  .dev = TIM4,
145  .rcc_mask = RCC_APB1ENR_TIM4EN,
146  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
147  { .pin = GPIO_UNDEF, .cc_chan = 0},
148  { .pin = GPIO_UNDEF, .cc_chan = 0},
149  { .pin = GPIO_UNDEF, .cc_chan = 0} },
150  .af = GPIO_AF2,
151  .bus = APB1
152  },
153 };
154 
155 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
156 
165 static const uint8_t spi_divtable[2][5] = {
166  { /* for APB1 @ 90000000Hz */
167  7, /* -> 351562Hz */
168  7, /* -> 351562Hz */
169  6, /* -> 703125Hz */
170  3, /* -> 5625000Hz */
171  2 /* -> 11250000Hz */
172  },
173  { /* for APB2 @ 180000000Hz */
174  7, /* -> 703125Hz */
175  7, /* -> 703125Hz */
176  7, /* -> 703125Hz */
177  4, /* -> 5625000Hz */
178  3 /* -> 11250000Hz */
179  }
180 };
181 
182 static const spi_conf_t spi_config[] = {
183  {
184  .dev = SPI1,
185  .mosi_pin = GPIO_PIN(PORT_A, 7),
186  .miso_pin = GPIO_PIN(PORT_A, 6),
187  .sclk_pin = GPIO_PIN(PORT_A, 5),
188  .cs_pin = GPIO_UNDEF,
189  .af = GPIO_AF5,
190  .rccmask = RCC_APB2ENR_SPI1EN,
191  .apbbus = APB2
192  }
193 };
194 
195 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
196 
202 #define I2C_NUMOF (1U)
203 #define I2C_0_EN 1
204 #define I2C_IRQ_PRIO 1
205 #define I2C_APBCLK (42000000U)
206 
207 /* I2C 0 device configuration */
208 #define I2C_0_DEV I2C1
209 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
210 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
211 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
212 #define I2C_0_EVT_ISR isr_i2c1_ev
213 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
214 #define I2C_0_ERR_ISR isr_i2c1_er
215 /* I2C 0 pin configuration */
216 #define I2C_0_SCL_PORT GPIOB
217 #define I2C_0_SCL_PIN 8
218 #define I2C_0_SCL_AF 4
219 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
220 #define I2C_0_SDA_PORT GPIOB
221 #define I2C_0_SDA_PIN 9
222 #define I2C_0_SDA_AF 4
223 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
224 
236 #define ADC_NUMOF (6U)
237 #define ADC_CONFIG { \
238  {GPIO_PIN(PORT_A, 3), 2, 3}, \
239  {GPIO_PIN(PORT_C, 0), 2, 10}, \
240  {GPIO_PIN(PORT_C, 3), 2, 13}, \
241  {GPIO_PIN(PORT_F, 3), 2, 9}, \
242  {GPIO_PIN(PORT_F, 5), 2, 15}, \
243  {GPIO_PIN(PORT_F, 10), 2, 8}, \
244 }
245 
247 #ifdef __cplusplus
248 }
249 #endif
250 
251 #endif /* PERIPH_CONF_H */
252 
use alternate function 7
USART_TypeDef * dev
USART device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.