boards/nucleo144-f429/include/periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 180MHz */
37 #define CLOCK_CORECLOCK (168000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (8000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (1)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
49 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
51 
52 /* Main PLL factors */
53 #define CLOCK_PLL_M (4)
54 #define CLOCK_PLL_N (168)
55 #define CLOCK_PLL_P (2)
56 #define CLOCK_PLL_Q (7)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM5,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM5EN,
68  .bus = APB1,
69  .irqn = TIM5_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim5
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART3,
85  .rcc_mask = RCC_APB1ENR_USART3EN,
86  .rx_pin = GPIO_PIN(PORT_D, 9),
87  .tx_pin = GPIO_PIN(PORT_D, 8),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB1,
91  .irqn = USART3_IRQn,
92 #ifdef UART_USE_DMA
93  .dma_stream = 6,
94  .dma_chan = 4
95 #endif
96  },
97  {
98  .dev = USART6,
99  .rcc_mask = RCC_APB2ENR_USART6EN,
100  .rx_pin = GPIO_PIN(PORT_G, 9),
101  .tx_pin = GPIO_PIN(PORT_G, 14),
102  .rx_af = GPIO_AF8,
103  .tx_af = GPIO_AF8,
104  .bus = APB2,
105  .irqn = USART6_IRQn,
106 #ifdef UART_USE_DMA
107  .dma_stream = 5,
108  .dma_chan = 4
109 #endif
110  },
111  {
112  .dev = USART2,
113  .rcc_mask = RCC_APB1ENR_USART2EN,
114  .rx_pin = GPIO_PIN(PORT_D, 6),
115  .tx_pin = GPIO_PIN(PORT_D, 5),
116  .rx_af = GPIO_AF7,
117  .tx_af = GPIO_AF7,
118  .bus = APB1,
119  .irqn = USART2_IRQn,
120 #ifdef UART_USE_DMA
121  .dma_stream = 4,
122  .dma_chan = 4
123 #endif
124  },
125 };
126 
127 #define UART_0_ISR (isr_usart3)
128 #define UART_0_DMA_ISR (isr_dma1_stream6)
129 #define UART_1_ISR (isr_usart6)
130 #define UART_1_DMA_ISR (isr_dma1_stream5)
131 #define UART_2_ISR (isr_usart2)
132 #define UART_2_DMA_ISR (isr_dma1_stream4)
133 
134 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
135 
141 static const pwm_conf_t pwm_config[] = {
142  {
143  .dev = TIM1,
144  .rcc_mask = RCC_APB2ENR_TIM1EN,
145  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
146  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
147  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
148  { .pin = GPIO_UNDEF, .cc_chan = 0} },
149  .af = GPIO_AF1,
150  .bus = APB2
151  },
152  {
153  .dev = TIM4,
154  .rcc_mask = RCC_APB1ENR_TIM4EN,
155  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
156  { .pin = GPIO_UNDEF, .cc_chan = 0},
157  { .pin = GPIO_UNDEF, .cc_chan = 0},
158  { .pin = GPIO_UNDEF, .cc_chan = 0} },
159  .af = GPIO_AF2,
160  .bus = APB1
161  },
162 };
163 
164 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
165 
174 static const uint8_t spi_divtable[2][5] = {
175  { /* for APB1 @ 90000000Hz */
176  7, /* -> 351562Hz */
177  7, /* -> 351562Hz */
178  6, /* -> 703125Hz */
179  3, /* -> 5625000Hz */
180  2 /* -> 11250000Hz */
181  },
182  { /* for APB2 @ 180000000Hz */
183  7, /* -> 703125Hz */
184  7, /* -> 703125Hz */
185  7, /* -> 703125Hz */
186  4, /* -> 5625000Hz */
187  3 /* -> 11250000Hz */
188  }
189 };
190 
191 static const spi_conf_t spi_config[] = {
192  {
193  .dev = SPI1,
194  .mosi_pin = GPIO_PIN(PORT_A, 7),
195  .miso_pin = GPIO_PIN(PORT_A, 6),
196  .sclk_pin = GPIO_PIN(PORT_A, 5),
197  .cs_pin = GPIO_UNDEF,
198  .af = GPIO_AF5,
199  .rccmask = RCC_APB2ENR_SPI1EN,
200  .apbbus = APB2
201  }
202 };
203 
204 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
205 
211 #define I2C_NUMOF (1U)
212 #define I2C_0_EN 1
213 #define I2C_IRQ_PRIO 1
214 #define I2C_APBCLK (42000000U)
215 
216 /* I2C 0 device configuration */
217 #define I2C_0_DEV I2C1
218 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
219 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
220 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
221 #define I2C_0_EVT_ISR isr_i2c1_ev
222 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
223 #define I2C_0_ERR_ISR isr_i2c1_er
224 /* I2C 0 pin configuration */
225 #define I2C_0_SCL_PORT GPIOB
226 #define I2C_0_SCL_PIN 8
227 #define I2C_0_SCL_AF 4
228 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
229 #define I2C_0_SDA_PORT GPIOB
230 #define I2C_0_SDA_PIN 9
231 #define I2C_0_SDA_AF 4
232 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
233 
245 #define ADC_NUMOF (6U)
246 #define ADC_CONFIG { \
247  {GPIO_PIN(PORT_A, 3), 2, 3}, \
248  {GPIO_PIN(PORT_C, 0), 2, 10}, \
249  {GPIO_PIN(PORT_C, 3), 2, 13}, \
250  {GPIO_PIN(PORT_F, 3), 2, 9}, \
251  {GPIO_PIN(PORT_F, 5), 2, 15}, \
252  {GPIO_PIN(PORT_F, 10), 2, 8}, \
253 }
254 
256 #ifdef __cplusplus
257 }
258 #endif
259 
260 #endif /* PERIPH_CONF_H */
261 
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.