boards/nucleo144-f429/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 180MHz */
39 #define CLOCK_CORECLOCK (168000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (8000000U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (1)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
53 
54 /* Main PLL factors */
55 #define CLOCK_PLL_M (4)
56 #define CLOCK_PLL_N (168)
57 #define CLOCK_PLL_P (2)
58 #define CLOCK_PLL_Q (7)
59 
65 static const timer_conf_t timer_config[] = {
66  {
67  .dev = TIM5,
68  .max = 0xffffffff,
69  .rcc_mask = RCC_APB1ENR_TIM5EN,
70  .bus = APB1,
71  .irqn = TIM5_IRQn
72  }
73 };
74 
75 #define TIMER_0_ISR isr_tim5
76 
77 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
78 
84 static const uart_conf_t uart_config[] = {
85  {
86  .dev = USART3,
87  .rcc_mask = RCC_APB1ENR_USART3EN,
88  .rx_pin = GPIO_PIN(PORT_D, 9),
89  .tx_pin = GPIO_PIN(PORT_D, 8),
90  .rx_af = GPIO_AF7,
91  .tx_af = GPIO_AF7,
92  .bus = APB1,
93  .irqn = USART3_IRQn,
94 #ifdef UART_USE_DMA
95  .dma_stream = 6,
96  .dma_chan = 4
97 #endif
98  },
99  {
100  .dev = USART6,
101  .rcc_mask = RCC_APB2ENR_USART6EN,
102  .rx_pin = GPIO_PIN(PORT_G, 9),
103  .tx_pin = GPIO_PIN(PORT_G, 14),
104  .rx_af = GPIO_AF8,
105  .tx_af = GPIO_AF8,
106  .bus = APB2,
107  .irqn = USART6_IRQn,
108 #ifdef UART_USE_DMA
109  .dma_stream = 5,
110  .dma_chan = 4
111 #endif
112  },
113  {
114  .dev = USART2,
115  .rcc_mask = RCC_APB1ENR_USART2EN,
116  .rx_pin = GPIO_PIN(PORT_D, 6),
117  .tx_pin = GPIO_PIN(PORT_D, 5),
118  .rx_af = GPIO_AF7,
119  .tx_af = GPIO_AF7,
120  .bus = APB1,
121  .irqn = USART2_IRQn,
122 #ifdef UART_USE_DMA
123  .dma_stream = 4,
124  .dma_chan = 4
125 #endif
126  },
127 };
128 
129 #define UART_0_ISR (isr_usart3)
130 #define UART_0_DMA_ISR (isr_dma1_stream6)
131 #define UART_1_ISR (isr_usart6)
132 #define UART_1_DMA_ISR (isr_dma1_stream5)
133 #define UART_2_ISR (isr_usart2)
134 #define UART_2_DMA_ISR (isr_dma1_stream4)
135 
136 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
137 
143 static const pwm_conf_t pwm_config[] = {
144  {
145  .dev = TIM1,
146  .rcc_mask = RCC_APB2ENR_TIM1EN,
147  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
148  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
149  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
150  { .pin = GPIO_UNDEF, .cc_chan = 0} },
151  .af = GPIO_AF1,
152  .bus = APB2
153  },
154  {
155  .dev = TIM4,
156  .rcc_mask = RCC_APB1ENR_TIM4EN,
157  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
158  { .pin = GPIO_UNDEF, .cc_chan = 0},
159  { .pin = GPIO_UNDEF, .cc_chan = 0},
160  { .pin = GPIO_UNDEF, .cc_chan = 0} },
161  .af = GPIO_AF2,
162  .bus = APB1
163  },
164 };
165 
166 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
167 
176 static const uint8_t spi_divtable[2][5] = {
177  { /* for APB1 @ 90000000Hz */
178  7, /* -> 351562Hz */
179  7, /* -> 351562Hz */
180  6, /* -> 703125Hz */
181  3, /* -> 5625000Hz */
182  2 /* -> 11250000Hz */
183  },
184  { /* for APB2 @ 180000000Hz */
185  7, /* -> 703125Hz */
186  7, /* -> 703125Hz */
187  7, /* -> 703125Hz */
188  4, /* -> 5625000Hz */
189  3 /* -> 11250000Hz */
190  }
191 };
192 
193 static const spi_conf_t spi_config[] = {
194  {
195  .dev = SPI1,
196  .mosi_pin = GPIO_PIN(PORT_A, 7),
197  .miso_pin = GPIO_PIN(PORT_A, 6),
198  .sclk_pin = GPIO_PIN(PORT_A, 5),
199  .cs_pin = GPIO_UNDEF,
200  .af = GPIO_AF5,
201  .rccmask = RCC_APB2ENR_SPI1EN,
202  .apbbus = APB2
203  }
204 };
205 
206 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
207 
213 #define I2C_NUMOF (1U)
214 #define I2C_0_EN 1
215 #define I2C_IRQ_PRIO 1
216 #define I2C_APBCLK (42000000U)
217 
218 /* I2C 0 device configuration */
219 #define I2C_0_DEV I2C1
220 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
221 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
222 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
223 #define I2C_0_EVT_ISR isr_i2c1_ev
224 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
225 #define I2C_0_ERR_ISR isr_i2c1_er
226 /* I2C 0 pin configuration */
227 #define I2C_0_SCL_PORT GPIOB
228 #define I2C_0_SCL_PIN 8
229 #define I2C_0_SCL_AF 4
230 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
231 #define I2C_0_SDA_PORT GPIOB
232 #define I2C_0_SDA_PIN 9
233 #define I2C_0_SDA_AF 4
234 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
235 
247 #define ADC_NUMOF (6U)
248 #define ADC_CONFIG { \
249  {GPIO_PIN(PORT_A, 3), 2, 3}, \
250  {GPIO_PIN(PORT_C, 0), 2, 10}, \
251  {GPIO_PIN(PORT_C, 3), 2, 13}, \
252  {GPIO_PIN(PORT_F, 3), 2, 9}, \
253  {GPIO_PIN(PORT_F, 5), 2, 15}, \
254  {GPIO_PIN(PORT_F, 10), 2, 8}, \
255 }
256 
258 #ifdef __cplusplus
259 }
260 #endif
261 
262 #endif /* PERIPH_CONF_H */
263 
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.