boards/nucleo144-f413/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  * Copyright (C) 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 100MHz */
39 #define CLOCK_CORECLOCK (100000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (8000000U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (1)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
53 
54 /* Main PLL factors */
55 #define CLOCK_PLL_M (4)
56 #define CLOCK_PLL_N (200)
57 #define CLOCK_PLL_P (4)
58 #define CLOCK_PLL_Q (0)
59 
60 /* PLL I2S configuration */
61 #define CLOCK_ENABLE_PLL_I2S (1)
62 #define CLOCK_PLL_I2S_SRC (0)
63 #define CLOCK_PLL_I2S_M (4)
64 #define CLOCK_PLL_I2S_N (216)
65 #define CLOCK_PLL_I2S_P (0)
66 #define CLOCK_PLL_I2S_Q (9)
67 
68 /* Use alternative source for 48MHz clock */
69 #define CLOCK_USE_ALT_48MHZ (1)
70 
76 static const timer_conf_t timer_config[] = {
77  {
78  .dev = TIM5,
79  .max = 0xffffffff,
80  .rcc_mask = RCC_APB1ENR_TIM5EN,
81  .bus = APB1,
82  .irqn = TIM5_IRQn
83  }
84 };
85 
86 #define TIMER_0_ISR isr_tim5
87 
88 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
89 
95 static const uart_conf_t uart_config[] = {
96  {
97  .dev = USART3,
98  .rcc_mask = RCC_APB1ENR_USART3EN,
99  .rx_pin = GPIO_PIN(PORT_D, 9),
100  .tx_pin = GPIO_PIN(PORT_D, 8),
101  .rx_af = GPIO_AF7,
102  .tx_af = GPIO_AF7,
103  .bus = APB1,
104  .irqn = USART3_IRQn,
105 #ifdef UART_USE_DMA
106  .dma_stream = 6,
107  .dma_chan = 4
108 #endif
109  },
110  {
111  .dev = USART6,
112  .rcc_mask = RCC_APB2ENR_USART6EN,
113  .rx_pin = GPIO_PIN(PORT_G, 9),
114  .tx_pin = GPIO_PIN(PORT_G, 14),
115  .rx_af = GPIO_AF8,
116  .tx_af = GPIO_AF8,
117  .bus = APB2,
118  .irqn = USART6_IRQn,
119 #ifdef UART_USE_DMA
120  .dma_stream = 5,
121  .dma_chan = 4
122 #endif
123  },
124  {
125  .dev = USART2,
126  .rcc_mask = RCC_APB1ENR_USART2EN,
127  .rx_pin = GPIO_PIN(PORT_D, 6),
128  .tx_pin = GPIO_PIN(PORT_D, 5),
129  .rx_af = GPIO_AF7,
130  .tx_af = GPIO_AF7,
131  .bus = APB1,
132  .irqn = USART2_IRQn,
133 #ifdef UART_USE_DMA
134  .dma_stream = 4,
135  .dma_chan = 4
136 #endif
137  },
138 };
139 
140 #define UART_0_ISR (isr_usart3)
141 #define UART_0_DMA_ISR (isr_dma1_stream6)
142 #define UART_1_ISR (isr_usart6)
143 #define UART_1_DMA_ISR (isr_dma1_stream5)
144 #define UART_2_ISR (isr_usart2)
145 #define UART_2_DMA_ISR (isr_dma1_stream4)
146 
147 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
148 
154 static const pwm_conf_t pwm_config[] = {
155  {
156  .dev = TIM1,
157  .rcc_mask = RCC_APB2ENR_TIM1EN,
158  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
159  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
160  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
161  { .pin = GPIO_UNDEF, .cc_chan = 0} },
162  .af = GPIO_AF1,
163  .bus = APB2
164  },
165  {
166  .dev = TIM4,
167  .rcc_mask = RCC_APB1ENR_TIM4EN,
168  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
169  { .pin = GPIO_UNDEF, .cc_chan = 0},
170  { .pin = GPIO_UNDEF, .cc_chan = 0},
171  { .pin = GPIO_UNDEF, .cc_chan = 0} },
172  .af = GPIO_AF2,
173  .bus = APB1
174  },
175 };
176 
177 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
178 
187 static const uint8_t spi_divtable[2][5] = {
188  { /* for APB1 @ 50000000Hz */
189  7, /* -> 195312Hz */
190  6, /* -> 390625Hz */
191  5, /* -> 781250Hz */
192  2, /* -> 6250000Hz */
193  1 /* -> 12500000Hz */
194  },
195  { /* for APB2 @ 100000000Hz */
196  7, /* -> 390625Hz */
197  7, /* -> 390625Hz */
198  6, /* -> 781250Hz */
199  3, /* -> 6250000Hz */
200  2 /* -> 12500000Hz */
201  }
202 };
203 
204 static const spi_conf_t spi_config[] = {
205  {
206  .dev = SPI1,
207  .mosi_pin = GPIO_PIN(PORT_A, 7),
208  .miso_pin = GPIO_PIN(PORT_A, 6),
209  .sclk_pin = GPIO_PIN(PORT_A, 5),
210  .cs_pin = GPIO_PIN(PORT_A, 4),
211  .af = GPIO_AF5,
212  .rccmask = RCC_APB2ENR_SPI1EN,
213  .apbbus = APB2
214  }
215 };
216 
217 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
218 
224 #define I2C_NUMOF (1U)
225 #define I2C_0_EN 1
226 #define I2C_IRQ_PRIO 1
227 #define I2C_APBCLK (CLOCK_APB1)
228 
229 /* I2C 0 device configuration */
230 #define I2C_0_DEV I2C1
231 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
232 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
233 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
234 #define I2C_0_EVT_ISR isr_i2c1_ev
235 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
236 #define I2C_0_ERR_ISR isr_i2c1_er
237 /* I2C 0 pin configuration */
238 #define I2C_0_SCL_PORT GPIOB
239 #define I2C_0_SCL_PIN 8
240 #define I2C_0_SCL_AF 4
241 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
242 #define I2C_0_SDA_PORT GPIOB
243 #define I2C_0_SDA_PIN 9
244 #define I2C_0_SDA_AF 4
245 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
246 
258 #define ADC_NUMOF (6U)
259 #define ADC_CONFIG { \
260  {GPIO_PIN(PORT_A, 3), 0, 3}, \
261  {GPIO_PIN(PORT_C, 0), 0, 10}, \
262  {GPIO_PIN(PORT_C, 3), 0, 13}, \
263  {GPIO_PIN(PORT_C, 1), 0, 11}, \
264  {GPIO_PIN(PORT_C, 4), 0, 14}, \
265  {GPIO_PIN(PORT_C, 5), 0, 15}, \
266 }
267 
273 #define RTC_NUMOF (1)
274 
276 #ifdef __cplusplus
277 }
278 #endif
279 
280 #endif /* PERIPH_CONF_H */
281 
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.