boards/nucleo144-f413/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  * Copyright (C) 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 /* 0: no external high speed crystal available
35  * else: actual crystal frequency [in Hz] */
36 #define CLOCK_HSE (8000000U)
37 /* 0: no external low speed crystal available,
38  * 1: external crystal available (always 32.768kHz) */
39 #define CLOCK_LSE (1)
40 /* give the target core clock (HCLK) frequency [in Hz],
41  * maximum: 100MHz */
42 #define CLOCK_CORECLOCK (96000000U)
43 /* peripheral clock setup */
44 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
45 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
46 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
47 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
48 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
49 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
50 
56 static const timer_conf_t timer_config[] = {
57  {
58  .dev = TIM5,
59  .max = 0xffffffff,
60  .rcc_mask = RCC_APB1ENR_TIM5EN,
61  .bus = APB1,
62  .irqn = TIM5_IRQn
63  }
64 };
65 
66 #define TIMER_0_ISR isr_tim5
67 
68 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
69 
75 static const uart_conf_t uart_config[] = {
76  {
77  .dev = USART3,
78  .rcc_mask = RCC_APB1ENR_USART3EN,
79  .rx_pin = GPIO_PIN(PORT_D, 9),
80  .tx_pin = GPIO_PIN(PORT_D, 8),
81  .rx_af = GPIO_AF7,
82  .tx_af = GPIO_AF7,
83  .bus = APB1,
84  .irqn = USART3_IRQn,
85 #ifdef UART_USE_DMA
86  .dma_stream = 6,
87  .dma_chan = 4
88 #endif
89  },
90  {
91  .dev = USART6,
92  .rcc_mask = RCC_APB2ENR_USART6EN,
93  .rx_pin = GPIO_PIN(PORT_G, 9),
94  .tx_pin = GPIO_PIN(PORT_G, 14),
95  .rx_af = GPIO_AF8,
96  .tx_af = GPIO_AF8,
97  .bus = APB2,
98  .irqn = USART6_IRQn,
99 #ifdef UART_USE_DMA
100  .dma_stream = 5,
101  .dma_chan = 4
102 #endif
103  },
104  {
105  .dev = USART2,
106  .rcc_mask = RCC_APB1ENR_USART2EN,
107  .rx_pin = GPIO_PIN(PORT_D, 6),
108  .tx_pin = GPIO_PIN(PORT_D, 5),
109  .rx_af = GPIO_AF7,
110  .tx_af = GPIO_AF7,
111  .bus = APB1,
112  .irqn = USART2_IRQn,
113 #ifdef UART_USE_DMA
114  .dma_stream = 4,
115  .dma_chan = 4
116 #endif
117  },
118 };
119 
120 #define UART_0_ISR (isr_usart3)
121 #define UART_0_DMA_ISR (isr_dma1_stream6)
122 #define UART_1_ISR (isr_usart6)
123 #define UART_1_DMA_ISR (isr_dma1_stream5)
124 #define UART_2_ISR (isr_usart2)
125 #define UART_2_DMA_ISR (isr_dma1_stream4)
126 
127 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
128 
134 static const pwm_conf_t pwm_config[] = {
135  {
136  .dev = TIM1,
137  .rcc_mask = RCC_APB2ENR_TIM1EN,
138  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
139  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
140  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
141  { .pin = GPIO_UNDEF, .cc_chan = 0} },
142  .af = GPIO_AF1,
143  .bus = APB2
144  },
145  {
146  .dev = TIM4,
147  .rcc_mask = RCC_APB1ENR_TIM4EN,
148  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
149  { .pin = GPIO_UNDEF, .cc_chan = 0},
150  { .pin = GPIO_UNDEF, .cc_chan = 0},
151  { .pin = GPIO_UNDEF, .cc_chan = 0} },
152  .af = GPIO_AF2,
153  .bus = APB1
154  },
155 };
156 
157 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
158 
167 static const uint8_t spi_divtable[2][5] = {
168  { /* for APB1 @ 50000000Hz */
169  7, /* -> 195312Hz */
170  6, /* -> 390625Hz */
171  5, /* -> 781250Hz */
172  2, /* -> 6250000Hz */
173  1 /* -> 12500000Hz */
174  },
175  { /* for APB2 @ 100000000Hz */
176  7, /* -> 390625Hz */
177  7, /* -> 390625Hz */
178  6, /* -> 781250Hz */
179  3, /* -> 6250000Hz */
180  2 /* -> 12500000Hz */
181  }
182 };
183 
184 static const spi_conf_t spi_config[] = {
185  {
186  .dev = SPI1,
187  .mosi_pin = GPIO_PIN(PORT_A, 7),
188  .miso_pin = GPIO_PIN(PORT_A, 6),
189  .sclk_pin = GPIO_PIN(PORT_A, 5),
190  .cs_pin = GPIO_PIN(PORT_A, 4),
191  .af = GPIO_AF5,
192  .rccmask = RCC_APB2ENR_SPI1EN,
193  .apbbus = APB2
194  }
195 };
196 
197 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
198 
204 #define I2C_NUMOF (1U)
205 #define I2C_0_EN 1
206 #define I2C_IRQ_PRIO 1
207 #define I2C_APBCLK (CLOCK_APB1)
208 
209 /* I2C 0 device configuration */
210 #define I2C_0_DEV I2C1
211 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
212 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
213 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
214 #define I2C_0_EVT_ISR isr_i2c1_ev
215 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
216 #define I2C_0_ERR_ISR isr_i2c1_er
217 /* I2C 0 pin configuration */
218 #define I2C_0_SCL_PORT GPIOB
219 #define I2C_0_SCL_PIN 8
220 #define I2C_0_SCL_AF 4
221 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
222 #define I2C_0_SDA_PORT GPIOB
223 #define I2C_0_SDA_PIN 9
224 #define I2C_0_SDA_AF 4
225 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
226 
238 #define ADC_NUMOF (6U)
239 #define ADC_CONFIG { \
240  {GPIO_PIN(PORT_A, 3), 0, 3}, \
241  {GPIO_PIN(PORT_C, 0), 0, 10}, \
242  {GPIO_PIN(PORT_C, 3), 0, 13}, \
243  {GPIO_PIN(PORT_C, 1), 0, 11}, \
244  {GPIO_PIN(PORT_C, 4), 0, 14}, \
245  {GPIO_PIN(PORT_C, 5), 0, 15}, \
246 }
247 
253 #define RTC_NUMOF (1)
254 
256 #ifdef __cplusplus
257 }
258 #endif
259 
260 #endif /* PERIPH_CONF_H */
261 
use alternate function 7
USART_TypeDef * dev
USART device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.