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boards/nucleo144-f413/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  * Copyright (C) 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define CLOCK_HSE (8000000U) /* external oscillator */
35 #define CLOCK_CORECLOCK (100000000U) /* desired core clock frequency */
36 
37 /* the actual PLL values are automatically generated */
38 #define CLOCK_PLL_M (CLOCK_HSE / 1000000)
39 #define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
40 #define CLOCK_PLL_P (2U)
41 #define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
42 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
43 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
44 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
45 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
46 
47 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
51 
57 static const timer_conf_t timer_config[] = {
58  {
59  .dev = TIM5,
60  .max = 0xffffffff,
61  .rcc_mask = RCC_APB1ENR_TIM5EN,
62  .bus = APB1,
63  .irqn = TIM5_IRQn
64  }
65 };
66 
67 #define TIMER_0_ISR isr_tim5
68 
69 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
70 
76 static const uart_conf_t uart_config[] = {
77  {
78  .dev = USART3,
79  .rcc_mask = RCC_APB1ENR_USART3EN,
80  .rx_pin = GPIO_PIN(PORT_D, 9),
81  .tx_pin = GPIO_PIN(PORT_D, 8),
82  .rx_af = GPIO_AF7,
83  .tx_af = GPIO_AF7,
84  .bus = APB1,
85  .irqn = USART3_IRQn,
86 #ifdef UART_USE_DMA
87  .dma_stream = 6,
88  .dma_chan = 4
89 #endif
90  },
91  {
92  .dev = USART2,
93  .rcc_mask = RCC_APB1ENR_USART2EN,
94  .rx_pin = GPIO_PIN(PORT_A, 3),
95  .tx_pin = GPIO_PIN(PORT_A, 2),
96  .rx_af = GPIO_AF7,
97  .tx_af = GPIO_AF7,
98  .bus = APB1,
99  .irqn = USART2_IRQn,
100 #ifdef UART_USE_DMA
101  .dma_stream = 5,
102  .dma_chan = 4
103 #endif
104  },
105  {
106  .dev = USART1,
107  .rcc_mask = RCC_APB2ENR_USART1EN,
108  .rx_pin = GPIO_PIN(PORT_A, 10),
109  .tx_pin = GPIO_PIN(PORT_A, 9),
110  .rx_af = GPIO_AF7,
111  .tx_af = GPIO_AF7,
112  .bus = APB2,
113  .irqn = USART1_IRQn,
114 #ifdef UART_USE_DMA
115  .dma_stream = 4,
116  .dma_chan = 4
117 #endif
118  },
119 };
120 
121 #define UART_0_ISR (isr_usart3)
122 #define UART_0_DMA_ISR (isr_dma1_stream6)
123 #define UART_1_ISR (isr_usart2)
124 #define UART_1_DMA_ISR (isr_dma1_stream5)
125 #define UART_2_ISR (isr_usart1)
126 #define UART_2_DMA_ISR (isr_dma1_stream4)
127 
128 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
129 
135 static const pwm_conf_t pwm_config[] = {
136  {
137  .dev = TIM2,
138  .rcc_mask = RCC_APB1ENR_TIM2EN,
139  .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
140  { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
141  { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
142  { .pin = GPIO_PIN(PORT_B, 2), .cc_chan = 3} },
143  .af = GPIO_AF1,
144  .bus = APB1
145  },
146  {
147  .dev = TIM3,
148  .rcc_mask = RCC_APB1ENR_TIM3EN,
149  .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
150  { .pin = GPIO_UNDEF, .cc_chan = 0 },
151  { .pin = GPIO_UNDEF, .cc_chan = 0 },
152  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
153  .af = GPIO_AF2,
154  .bus = APB1
155  },
156  {
157  .dev = TIM8,
158  .rcc_mask = RCC_APB2ENR_TIM8EN,
159  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
160  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
161  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
162  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
163  .af = GPIO_AF3,
164  .bus = APB2
165  },
166 };
167 
168 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
169 
178 static const uint8_t spi_divtable[2][5] = {
179  { /* for APB1 @ 50000000Hz */
180  7, /* -> 195312Hz */
181  6, /* -> 390625Hz */
182  5, /* -> 781250Hz */
183  2, /* -> 6250000Hz */
184  1 /* -> 12500000Hz */
185  },
186  { /* for APB2 @ 100000000Hz */
187  7, /* -> 390625Hz */
188  7, /* -> 390625Hz */
189  6, /* -> 781250Hz */
190  3, /* -> 6250000Hz */
191  2 /* -> 12500000Hz */
192  }
193 };
194 
195 
196 
197 static const spi_conf_t spi_config[] = {
198  {
199  .dev = SPI1,
200  .mosi_pin = GPIO_PIN(PORT_A, 7),
201  .miso_pin = GPIO_PIN(PORT_A, 6),
202  .sclk_pin = GPIO_PIN(PORT_A, 5),
203  .cs_pin = GPIO_PIN(PORT_A, 4),
204  .af = GPIO_AF5,
205  .rccmask = RCC_APB2ENR_SPI1EN,
206  .apbbus = APB2
207  }
208 };
209 
210 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
211 
218 #define I2C_NUMOF (1U)
219 #define I2C_0_EN 1
220 #define I2C_IRQ_PRIO 1
221 #define I2C_APBCLK (42000000U)
222 
223 /* I2C 0 device configuration */
224 #define I2C_0_DEV I2C1
225 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
226 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
227 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
228 #define I2C_0_EVT_ISR isr_i2c1_ev
229 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
230 #define I2C_0_ERR_ISR isr_i2c1_er
231 /* I2C 0 pin configuration */
232 #define I2C_0_SCL_PORT GPIOB
233 #define I2C_0_SCL_PIN 8
234 #define I2C_0_SCL_AF 4
235 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
236 #define I2C_0_SDA_PORT GPIOB
237 #define I2C_0_SDA_PIN 9
238 #define I2C_0_SDA_AF 4
239 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
240 
246 #define ADC_NUMOF (0)
247 
253 #define DAC_NUMOF (0)
254 
260 #define RTC_NUMOF (1)
261 
263 #ifdef __cplusplus
264 }
265 #endif
266 
267 #endif /* PERIPH_CONF_H */
268 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 3
use alternate function 1
PWM configuration structure.
static const pwm_conf_t pwm_config[]
PWM configuration.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
static const timer_conf_t timer_config[]
Timer configuration.
cc2538_ssi_t * dev
SSI device.