boards/nucleo144-f413/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  * Copyright (C) 2017 OTA keys S.A.
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
23 #ifndef PERIPH_CONF_H
24 #define PERIPH_CONF_H
25 
26 #include "periph_cpu.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
39 /* give the target core clock (HCLK) frequency [in Hz],
40  * maximum: 100MHz */
41 #define CLOCK_CORECLOCK (100000000U)
42 /* 0: no external high speed crystal available
43  * else: actual crystal frequency [in Hz] */
44 #define CLOCK_HSE (8000000U)
45 /* 0: no external low speed crystal available,
46  * 1: external crystal available (always 32.768kHz) */
47 #define CLOCK_LSE (1)
48 /* peripheral clock setup */
49 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
50 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
51 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
52 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
53 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
54 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
55 
56 /* Main PLL factors */
57 #define CLOCK_PLL_M (4)
58 #define CLOCK_PLL_N (200)
59 #define CLOCK_PLL_P (4)
60 #define CLOCK_PLL_Q (0)
61 
62 /* PLL I2S configuration */
63 #define CLOCK_ENABLE_PLL_I2S (1)
64 #define CLOCK_PLL_I2S_SRC (0)
65 #define CLOCK_PLL_I2S_M (4)
66 #define CLOCK_PLL_I2S_N (216)
67 #define CLOCK_PLL_I2S_P (0)
68 #define CLOCK_PLL_I2S_Q (9)
69 
70 /* Use alternative source for 48MHz clock */
71 #define CLOCK_USE_ALT_48MHZ (1)
72 
78 static const timer_conf_t timer_config[] = {
79  {
80  .dev = TIM5,
81  .max = 0xffffffff,
82  .rcc_mask = RCC_APB1ENR_TIM5EN,
83  .bus = APB1,
84  .irqn = TIM5_IRQn
85  }
86 };
87 
88 #define TIMER_0_ISR isr_tim5
89 
90 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
91 
97 static const uart_conf_t uart_config[] = {
98  {
99  .dev = USART3,
100  .rcc_mask = RCC_APB1ENR_USART3EN,
101  .rx_pin = GPIO_PIN(PORT_D, 9),
102  .tx_pin = GPIO_PIN(PORT_D, 8),
103  .rx_af = GPIO_AF7,
104  .tx_af = GPIO_AF7,
105  .bus = APB1,
106  .irqn = USART3_IRQn,
107 #ifdef UART_USE_DMA
108  .dma_stream = 6,
109  .dma_chan = 4
110 #endif
111  },
112  {
113  .dev = USART6,
114  .rcc_mask = RCC_APB2ENR_USART6EN,
115  .rx_pin = GPIO_PIN(PORT_G, 9),
116  .tx_pin = GPIO_PIN(PORT_G, 14),
117  .rx_af = GPIO_AF8,
118  .tx_af = GPIO_AF8,
119  .bus = APB2,
120  .irqn = USART6_IRQn,
121 #ifdef UART_USE_DMA
122  .dma_stream = 5,
123  .dma_chan = 4
124 #endif
125  },
126  {
127  .dev = USART2,
128  .rcc_mask = RCC_APB1ENR_USART2EN,
129  .rx_pin = GPIO_PIN(PORT_D, 6),
130  .tx_pin = GPIO_PIN(PORT_D, 5),
131  .rx_af = GPIO_AF7,
132  .tx_af = GPIO_AF7,
133  .bus = APB1,
134  .irqn = USART2_IRQn,
135 #ifdef UART_USE_DMA
136  .dma_stream = 4,
137  .dma_chan = 4
138 #endif
139  },
140 };
141 
142 #define UART_0_ISR (isr_usart3)
143 #define UART_0_DMA_ISR (isr_dma1_stream6)
144 #define UART_1_ISR (isr_usart6)
145 #define UART_1_DMA_ISR (isr_dma1_stream5)
146 #define UART_2_ISR (isr_usart2)
147 #define UART_2_DMA_ISR (isr_dma1_stream4)
148 
149 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
150 
156 static const pwm_conf_t pwm_config[] = {
157  {
158  .dev = TIM1,
159  .rcc_mask = RCC_APB2ENR_TIM1EN,
160  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
161  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
162  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
163  { .pin = GPIO_UNDEF, .cc_chan = 0} },
164  .af = GPIO_AF1,
165  .bus = APB2
166  },
167  {
168  .dev = TIM4,
169  .rcc_mask = RCC_APB1ENR_TIM4EN,
170  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
171  { .pin = GPIO_UNDEF, .cc_chan = 0},
172  { .pin = GPIO_UNDEF, .cc_chan = 0},
173  { .pin = GPIO_UNDEF, .cc_chan = 0} },
174  .af = GPIO_AF2,
175  .bus = APB1
176  },
177 };
178 
179 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
180 
189 static const uint8_t spi_divtable[2][5] = {
190  { /* for APB1 @ 50000000Hz */
191  7, /* -> 195312Hz */
192  6, /* -> 390625Hz */
193  5, /* -> 781250Hz */
194  2, /* -> 6250000Hz */
195  1 /* -> 12500000Hz */
196  },
197  { /* for APB2 @ 100000000Hz */
198  7, /* -> 390625Hz */
199  7, /* -> 390625Hz */
200  6, /* -> 781250Hz */
201  3, /* -> 6250000Hz */
202  2 /* -> 12500000Hz */
203  }
204 };
205 
206 static const spi_conf_t spi_config[] = {
207  {
208  .dev = SPI1,
209  .mosi_pin = GPIO_PIN(PORT_A, 7),
210  .miso_pin = GPIO_PIN(PORT_A, 6),
211  .sclk_pin = GPIO_PIN(PORT_A, 5),
212  .cs_pin = GPIO_PIN(PORT_A, 4),
213  .af = GPIO_AF5,
214  .rccmask = RCC_APB2ENR_SPI1EN,
215  .apbbus = APB2
216  }
217 };
218 
219 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
220 
226 #define I2C_NUMOF (1U)
227 #define I2C_0_EN 1
228 #define I2C_IRQ_PRIO 1
229 #define I2C_APBCLK (CLOCK_APB1)
230 
231 /* I2C 0 device configuration */
232 #define I2C_0_DEV I2C1
233 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
234 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
235 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
236 #define I2C_0_EVT_ISR isr_i2c1_ev
237 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
238 #define I2C_0_ERR_ISR isr_i2c1_er
239 /* I2C 0 pin configuration */
240 #define I2C_0_SCL_PORT GPIOB
241 #define I2C_0_SCL_PIN 8
242 #define I2C_0_SCL_AF 4
243 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
244 #define I2C_0_SDA_PORT GPIOB
245 #define I2C_0_SDA_PIN 9
246 #define I2C_0_SDA_AF 4
247 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
248 
260 #define ADC_NUMOF (6U)
261 #define ADC_CONFIG { \
262  {GPIO_PIN(PORT_A, 3), 0, 3}, \
263  {GPIO_PIN(PORT_C, 0), 0, 10}, \
264  {GPIO_PIN(PORT_C, 3), 0, 13}, \
265  {GPIO_PIN(PORT_C, 1), 0, 11}, \
266  {GPIO_PIN(PORT_C, 4), 0, 14}, \
267  {GPIO_PIN(PORT_C, 5), 0, 15}, \
268 }
269 
275 #define RTC_NUMOF (1)
276 
282 #define RTT_NUMOF (1)
283 #define RTT_FREQUENCY (4096)
284 #define RTT_MAX_VALUE (0xffff)
285 
287 #ifdef __cplusplus
288 }
289 #endif
290 
291 #endif /* PERIPH_CONF_H */
292 
use alternate function 7
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
use alternate function 8
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.