boards/nucleo144-f303/include/periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2017 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 72MHz */
37 #define CLOCK_CORECLOCK (72000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (8000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (1)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
49 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
51 
52 /* PLL factors */
53 #define CLOCK_PLL_PREDIV (1)
54 #define CLOCK_PLL_MUL (9)
55 
61 static const timer_conf_t timer_config[] = {
62  {
63  .dev = TIM2,
64  .max = 0xffffffff,
65  .rcc_mask = RCC_APB1ENR_TIM2EN,
66  .bus = APB1,
67  .irqn = TIM2_IRQn
68  }
69 };
70 
71 #define TIMER_0_ISR isr_tim2
72 
73 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
74 
80 static const uart_conf_t uart_config[] = {
81  {
82  .dev = USART3,
83  .rcc_mask = RCC_APB1ENR_USART3EN,
84  .rx_pin = GPIO_PIN(PORT_D, 9),
85  .tx_pin = GPIO_PIN(PORT_D, 8),
86  .rx_af = GPIO_AF7,
87  .tx_af = GPIO_AF7,
88  .bus = APB1,
89  .irqn = USART3_IRQn,
90 #ifdef UART_USE_DMA
91  .dma_stream = 6,
92  .dma_chan = 4
93 #endif
94  },
95  {
96  .dev = USART1,
97  .rcc_mask = RCC_APB2ENR_USART1EN,
98  .rx_pin = GPIO_PIN(PORT_C, 5),
99  .tx_pin = GPIO_PIN(PORT_C, 4),
100  .rx_af = GPIO_AF7,
101  .tx_af = GPIO_AF7,
102  .bus = APB2,
103  .irqn = USART1_IRQn,
104 #ifdef UART_USE_DMA
105  .dma_stream = 5,
106  .dma_chan = 4
107 #endif
108  },
109  {
110  .dev = USART2,
111  .rcc_mask = RCC_APB1ENR_USART2EN,
112  .rx_pin = GPIO_PIN(PORT_D, 6),
113  .tx_pin = GPIO_PIN(PORT_D, 5),
114  .rx_af = GPIO_AF7,
115  .tx_af = GPIO_AF7,
116  .bus = APB1,
117  .irqn = USART2_IRQn,
118 #ifdef UART_USE_DMA
119  .dma_stream = 4,
120  .dma_chan = 4
121 #endif
122  },
123 };
124 
125 #define UART_0_ISR (isr_usart3)
126 #define UART_0_DMA_ISR (isr_dma1_stream6)
127 #define UART_1_ISR (isr_usart1)
128 #define UART_1_DMA_ISR (isr_dma1_stream5)
129 #define UART_2_ISR (isr_usart2)
130 #define UART_2_DMA_ISR (isr_dma1_stream4)
131 
132 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
133 
139 static const pwm_conf_t pwm_config[] = {
140  {
141  .dev = TIM1,
142  .rcc_mask = RCC_APB2ENR_TIM1EN,
143  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
144  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
145  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
146  { .pin = GPIO_UNDEF, .cc_chan = 0} },
147  .af = GPIO_AF2,
148  .bus = APB2
149  },
150  {
151  .dev = TIM4,
152  .rcc_mask = RCC_APB1ENR_TIM4EN,
153  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
154  { .pin = GPIO_UNDEF, .cc_chan = 0},
155  { .pin = GPIO_UNDEF, .cc_chan = 0},
156  { .pin = GPIO_UNDEF, .cc_chan = 0} },
157  .af = GPIO_AF2,
158  .bus = APB1
159  }
160 };
161 
162 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
163 
172 static const uint8_t spi_divtable[2][5] = {
173  { /* for APB1 @ 36000000Hz */
174  7, /* -> 140625Hz */
175  6, /* -> 281250Hz */
176  4, /* -> 1125000Hz */
177  2, /* -> 4500000Hz */
178  1 /* -> 9000000Hz */
179  },
180  { /* for APB2 @ 72000000Hz */
181  7, /* -> 281250Hz */
182  7, /* -> 281250Hz */
183  5, /* -> 1125000Hz */
184  3, /* -> 4500000Hz */
185  2 /* -> 9000000Hz */
186  }
187 };
188 
189 static const spi_conf_t spi_config[] = {
190  {
191  .dev = SPI1,
192  .mosi_pin = GPIO_PIN(PORT_A, 7),
193  .miso_pin = GPIO_PIN(PORT_A, 6),
194  .sclk_pin = GPIO_PIN(PORT_A, 5),
195  .cs_pin = GPIO_UNDEF,
196  .af = GPIO_AF5,
197  .rccmask = RCC_APB2ENR_SPI1EN,
198  .apbbus = APB2
199  }
200 };
201 
202 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
203 
210 #define I2C_NUMOF (0U)
211 
217 #define ADC_NUMOF (0)
218 
220 #ifdef __cplusplus
221 }
222 #endif
223 
224 #endif /* PERIPH_CONF_H */
225 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
PWM configuration structure.
NRF_TIMER_Type * dev
timer device
use alternate function 5
Tcc * dev
TCC device to use.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.