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boards/nucleo144-f207/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016-2017 OTA keys S.A.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define CLOCK_HSE (8000000U) /* external oscillator */
35 #define CLOCK_CORECLOCK (120000000U) /* desired core clock frequency */
36 
37 /* the actual PLL values are automatically generated */
38 #define CLOCK_PLL_M (CLOCK_HSE / 1000000)
39 #define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
40 #define CLOCK_PLL_P (2U)
41 #define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
42 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
43 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
44 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
45 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
46 
47 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
51 
57 static const pwm_conf_t pwm_config[] = {
58  {
59  .dev = TIM3,
60  .rcc_mask = RCC_APB1ENR_TIM3EN,
61  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0 },
62  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1 },
63  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
64  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
65  .af = GPIO_AF2,
66  .bus = APB1
67  }
68 };
69 
70 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
71 
77 static const timer_conf_t timer_config[] = {
78  {
79  .dev = TIM2,
80  .max = 0xffffffff,
81  .rcc_mask = RCC_APB1ENR_TIM2EN,
82  .bus = APB1,
83  .irqn = TIM2_IRQn
84  },
85  {
86  .dev = TIM5,
87  .max = 0xffffffff,
88  .rcc_mask = RCC_APB1ENR_TIM5EN,
89  .bus = APB1,
90  .irqn = TIM5_IRQn
91  },
92  {
93  .dev = TIM4,
94  .max = 0xffffffff,
95  .rcc_mask = RCC_APB1ENR_TIM4EN,
96  .bus = APB1,
97  .irqn = TIM4_IRQn
98  }
99 };
100 
101 #define TIMER_0_ISR isr_tim2
102 #define TIMER_1_ISR isr_tim5
103 #define TIMER_2_ISR isr_tim3
104 #define TIMER_3_ISR isr_tim4
105 
106 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
107 
112 static const uart_conf_t uart_config[] = {
113  {
114  .dev = USART3,
115  .rcc_mask = RCC_APB1ENR_USART3EN,
116  .rx_pin = GPIO_PIN(PORT_D, 9),
117  .tx_pin = GPIO_PIN(PORT_D, 8),
118  .rx_af = GPIO_AF7,
119  .tx_af = GPIO_AF7,
120  .bus = APB1,
121  .irqn = USART3_IRQn,
122 #ifdef UART_USE_DMA
123  .dma_stream = 3,
124  .dma_chan = 4
125 #endif
126  },
127  {
128  .dev = USART2,
129  .rcc_mask = RCC_APB1ENR_USART2EN,
130  .rx_pin = GPIO_PIN(PORT_D, 6),
131  .tx_pin = GPIO_PIN(PORT_D, 5),
132  .rx_af = GPIO_AF7,
133  .tx_af = GPIO_AF7,
134  .bus = APB1,
135  .irqn = USART2_IRQn,
136 #ifdef UART_USE_DMA
137  .dma_stream = 6,
138  .dma_chan = 4
139 #endif
140  },
141  {
142  .dev = USART1,
143  .rcc_mask = RCC_APB2ENR_USART1EN,
144  .rx_pin = GPIO_PIN(PORT_A, 10),
145  .tx_pin = GPIO_PIN(PORT_A, 9),
146  .rx_af = GPIO_AF7,
147  .tx_af = GPIO_AF7,
148  .bus = APB2,
149  .irqn = USART1_IRQn,
150 #ifdef UART_USE_DMA
151  .dma_stream = 7,
152  .dma_chan = 4
153 #endif
154  }
155 };
156 
157 #define UART_0_ISR (isr_usart3)
158 #define UART_0_DMA_ISR (isr_dma1_stream3)
159 
160 #define UART_1_ISR (isr_usart2)
161 #define UART_1_DMA_ISR (isr_dma1_stream6)
162 
163 #define UART_2_ISR (isr_usart1)
164 #define UART_2_DMA_ISR (isr_dma1_stream7)
165 
166 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
167 
176 static const uint8_t spi_divtable[2][5] = {
177  { /* for APB1 @ 30000000Hz */
178  7, /* -> 117187Hz */
179  5, /* -> 468750Hz */
180  4, /* -> 937500Hz */
181  2, /* -> 3750000Hz */
182  1 /* -> 7500000Hz */
183  },
184  { /* for APB2 @ 60000000Hz */
185  7, /* -> 234375Hz */
186  6, /* -> 468750Hz */
187  5, /* -> 937500Hz */
188  3, /* -> 3750000Hz */
189  2 /* -> 7500000Hz */
190  }
191 };
192 
193 static const spi_conf_t spi_config[] = {
194  {
195  .dev = SPI1,
196  .mosi_pin = GPIO_PIN(PORT_A, 7),
197  .miso_pin = GPIO_PIN(PORT_A, 6),
198  .sclk_pin = GPIO_PIN(PORT_A, 5),
199  .cs_pin = GPIO_PIN(PORT_A, 4),
200  .af = GPIO_AF5,
201  .rccmask = RCC_APB2ENR_SPI1EN,
202  .apbbus = APB2
203  },
204  {
205  .dev = SPI2,
206  .mosi_pin = GPIO_PIN(PORT_B, 15),
207  .miso_pin = GPIO_PIN(PORT_C, 2),
208  .sclk_pin = GPIO_PIN(PORT_B, 13),
209  .cs_pin = GPIO_PIN(PORT_B, 12),
210  .af = GPIO_AF5,
211  .rccmask = RCC_APB1ENR_SPI2EN,
212  .apbbus = APB1
213  }
214 };
215 
216 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
217 
223 #define I2C_NUMOF (1U)
224 #define I2C_0_EN 1
225 #define I2C_IRQ_PRIO 1
226 #define I2C_APBCLK (CLOCK_APB1)
227 
228 /* I2C 0 device configuration */
229 #define I2C_0_DEV I2C1
230 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
231 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
232 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
233 #define I2C_0_EVT_ISR isr_i2c1_ev
234 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
235 #define I2C_0_ERR_ISR isr_i2c1_er
236 /* I2C 0 pin configuration */
237 #define I2C_0_SCL_PORT GPIOB
238 #define I2C_0_SCL_PIN 8
239 #define I2C_0_SCL_AF 4
240 #define I2C_0_SCL_PULLUP 0
241 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
242 #define I2C_0_SDA_PORT GPIOB
243 #define I2C_0_SDA_PIN 9
244 #define I2C_0_SDA_AF 4
245 #define I2C_0_SDA_PULLUP 0
246 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
247 
256 #define ADC_CONFIG { \
257  {GPIO_PIN(PORT_A, 3), 0, 3}, \
258  {GPIO_PIN(PORT_C, 0), 1, 0} \
259 }
260 #define ADC_NUMOF (2)
261 
268 #define DAC_NUMOF (0)
269 
275 #define RTC_NUMOF (1)
276 
278 #ifdef __cplusplus
279 }
280 #endif
281 
282 #endif /* PERIPH_CONF_H */
283 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.