boards/nucleo144-f207/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016-2017 OTA keys S.A.
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 /* 0: no external high speed crystal available
35  * else: actual crystal frequency [in Hz] */
36 #define CLOCK_HSE (8000000U)
37 /* 0: no external low speed crystal available,
38  * 1: external crystal available (always 32.768kHz) */
39 #define CLOCK_LSE (1)
40 /* give the target core clock (HCLK) frequency [in Hz],
41  * maximum: 120MHz */
42 #define CLOCK_CORECLOCK (120000000U)
43 /* peripheral clock setup */
44 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
45 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
46 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 30MHz */
47 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
48 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 60MHz */
49 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
50 
56 static const pwm_conf_t pwm_config[] = {
57  {
58  .dev = TIM1,
59  .rcc_mask = RCC_APB2ENR_TIM1EN,
60  .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0},
61  { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1},
62  { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2},
63  { .pin = GPIO_UNDEF, .cc_chan = 0} },
64  .af = GPIO_AF1,
65  .bus = APB2
66  },
67  {
68  .dev = TIM4,
69  .rcc_mask = RCC_APB1ENR_TIM4EN,
70  .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3},
71  { .pin = GPIO_UNDEF, .cc_chan = 0},
72  { .pin = GPIO_UNDEF, .cc_chan = 0},
73  { .pin = GPIO_UNDEF, .cc_chan = 0} },
74  .af = GPIO_AF2,
75  .bus = APB1
76  },
77 };
78 
79 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
80 
86 static const timer_conf_t timer_config[] = {
87  {
88  .dev = TIM2,
89  .max = 0xffffffff,
90  .rcc_mask = RCC_APB1ENR_TIM2EN,
91  .bus = APB1,
92  .irqn = TIM2_IRQn
93  },
94  {
95  .dev = TIM5,
96  .max = 0xffffffff,
97  .rcc_mask = RCC_APB1ENR_TIM5EN,
98  .bus = APB1,
99  .irqn = TIM5_IRQn
100  }
101 };
102 
103 #define TIMER_0_ISR isr_tim2
104 #define TIMER_1_ISR isr_tim5
105 
106 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
107 
113 static const uart_conf_t uart_config[] = {
114  {
115  .dev = USART3,
116  .rcc_mask = RCC_APB1ENR_USART3EN,
117  .rx_pin = GPIO_PIN(PORT_D, 9),
118  .tx_pin = GPIO_PIN(PORT_D, 8),
119  .rx_af = GPIO_AF7,
120  .tx_af = GPIO_AF7,
121  .bus = APB1,
122  .irqn = USART3_IRQn,
123 #ifdef UART_USE_DMA
124  .dma_stream = 3,
125  .dma_chan = 4
126 #endif
127  },
128  {
129  .dev = USART6,
130  .rcc_mask = RCC_APB2ENR_USART6EN,
131  .rx_pin = GPIO_PIN(PORT_G, 9),
132  .tx_pin = GPIO_PIN(PORT_G, 14),
133  .rx_af = GPIO_AF8,
134  .tx_af = GPIO_AF8,
135  .bus = APB2,
136  .irqn = USART6_IRQn,
137 #ifdef UART_USE_DMA
138  .dma_stream = 6,
139  .dma_chan = 4
140 #endif
141  },
142  {
143  .dev = USART2,
144  .rcc_mask = RCC_APB1ENR_USART2EN,
145  .rx_pin = GPIO_PIN(PORT_D, 6),
146  .tx_pin = GPIO_PIN(PORT_D, 5),
147  .rx_af = GPIO_AF7,
148  .tx_af = GPIO_AF7,
149  .bus = APB1,
150  .irqn = USART2_IRQn,
151 #ifdef UART_USE_DMA
152  .dma_stream = 7,
153  .dma_chan = 4
154 #endif
155  },
156 };
157 
158 #define UART_0_ISR (isr_usart3)
159 #define UART_0_DMA_ISR (isr_dma1_stream3)
160 
161 #define UART_1_ISR (isr_usart6)
162 #define UART_1_DMA_ISR (isr_dma1_stream6)
163 
164 #define UART_2_ISR (isr_usart2)
165 #define UART_2_DMA_ISR (isr_dma1_stream7)
166 
167 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
168 
177 static const uint8_t spi_divtable[2][5] = {
178  { /* for APB1 @ 30000000Hz */
179  7, /* -> 117187Hz */
180  5, /* -> 468750Hz */
181  4, /* -> 937500Hz */
182  2, /* -> 3750000Hz */
183  1 /* -> 7500000Hz */
184  },
185  { /* for APB2 @ 60000000Hz */
186  7, /* -> 234375Hz */
187  6, /* -> 468750Hz */
188  5, /* -> 937500Hz */
189  3, /* -> 3750000Hz */
190  2 /* -> 7500000Hz */
191  }
192 };
193 
194 static const spi_conf_t spi_config[] = {
195  {
196  .dev = SPI1,
197  .mosi_pin = GPIO_PIN(PORT_A, 7),
198  .miso_pin = GPIO_PIN(PORT_A, 6),
199  .sclk_pin = GPIO_PIN(PORT_A, 5),
200  .cs_pin = GPIO_PIN(PORT_A, 4),
201  .af = GPIO_AF5,
202  .rccmask = RCC_APB2ENR_SPI1EN,
203  .apbbus = APB2
204  },
205  {
206  .dev = SPI2,
207  .mosi_pin = GPIO_PIN(PORT_B, 15),
208  .miso_pin = GPIO_PIN(PORT_C, 2),
209  .sclk_pin = GPIO_PIN(PORT_B, 13),
210  .cs_pin = GPIO_PIN(PORT_B, 12),
211  .af = GPIO_AF5,
212  .rccmask = RCC_APB1ENR_SPI2EN,
213  .apbbus = APB1
214  }
215 };
216 
217 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
218 
224 #define I2C_NUMOF (1U)
225 #define I2C_0_EN 1
226 #define I2C_IRQ_PRIO 1
227 #define I2C_APBCLK (CLOCK_APB1)
228 
229 /* I2C 0 device configuration */
230 #define I2C_0_DEV I2C1
231 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
232 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
233 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
234 #define I2C_0_EVT_ISR isr_i2c1_ev
235 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
236 #define I2C_0_ERR_ISR isr_i2c1_er
237 /* I2C 0 pin configuration */
238 #define I2C_0_SCL_PORT GPIOB
239 #define I2C_0_SCL_PIN 8
240 #define I2C_0_SCL_AF 4
241 #define I2C_0_SCL_PULLUP 0
242 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
243 #define I2C_0_SDA_PORT GPIOB
244 #define I2C_0_SDA_PIN 9
245 #define I2C_0_SDA_AF 4
246 #define I2C_0_SDA_PULLUP 0
247 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
248 
257 #define ADC_CONFIG { \
258  {GPIO_PIN(PORT_A, 3), 0, 3}, \
259  {GPIO_PIN(PORT_C, 0), 1, 0} \
260 }
261 #define ADC_NUMOF (2)
262 
268 #define RTC_NUMOF (1)
269 
271 #ifdef __cplusplus
272 }
273 #endif
274 
275 #endif /* PERIPH_CONF_H */
276 
use alternate function 7
USART_TypeDef * dev
USART device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.