boards/nucleo-l476/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Freie Universit├Ąt Berlin
3  * 2017 Inria
4  * 2017 HAW-Hamburg
5  *
6  * This file is subject to the terms and conditions of the GNU Lesser
7  * General Public License v2.1. See the file LICENSE in the top level
8  * directory for more details.
9  */
10 
25 #ifndef PERIPH_CONF_H
26 #define PERIPH_CONF_H
27 
28 #include "periph_cpu.h"
29 
30 #ifdef __cplusplus
31 extern "C" {
32 #endif
33 
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (0)
41 
42 #ifndef CLOCK_LSE
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz)
45  * This defaults to 0 because hardware revision 'MB1136 C-01' of the nucleo-64
46  * board disconnects LSE by default. You may safely set this to 1 on revisions
47  * newer than 'MB1136 C-01' */
48 #define CLOCK_LSE (0)
49 #endif
50 
51 /* 0: enable MSI only if HSE isn't available
52  * 1: always enable MSI (e.g. if USB or RNG is used)*/
53 #define CLOCK_MSI_ENABLE (1)
54 
55 #ifndef CLOCK_MSI_LSE_PLL
56 /* 0: disable Hardware auto calibration with LSE
57  * 1: enable Hardware auto calibration with LSE (PLL-mode)
58  * Same as with CLOCK_LSE above this defaults to 0 because LSE is
59  * mandatory for MSI/LSE-trimming to work */
60 #define CLOCK_MSI_LSE_PLL (0)
61 #endif
62 
63 /* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
64 #define CLOCK_CORECLOCK (80000000U)
65 /* PLL configuration: make sure your values are legit!
66  *
67  * compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
68  * with:
69  * PLL_IN: input clock, HSE or MSI @ 48MHz
70  * M: pre-divider, allowed range: [1:8]
71  * N: multiplier, allowed range: [8:86]
72  * R: post-divider, allowed range: [2,4,6,8]
73  *
74  * Also the following constraints need to be met:
75  * (PLL_IN / M) -> [4MHz:16MHz]
76  * (PLL_IN / M) * N -> [64MHz:344MHz]
77  * CORECLOCK -> 80MHz MAX!
78  */
79 #define CLOCK_PLL_M (6)
80 #define CLOCK_PLL_N (20)
81 #define CLOCK_PLL_R (2)
82 /* peripheral clock setup */
83 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
84 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
85 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
86 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
87 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
88 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
89 
95 static const timer_conf_t timer_config[] = {
96  {
97  .dev = TIM5,
98  .max = 0xffffffff,
99  .rcc_mask = RCC_APB1ENR1_TIM5EN,
100  .bus = APB1,
101  .irqn = TIM5_IRQn
102  }
103 };
104 
105 #define TIMER_0_ISR isr_tim5
106 
107 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
108 
114 static const uart_conf_t uart_config[] = {
115  {
116  .dev = USART2,
117  .rcc_mask = RCC_APB1ENR1_USART2EN,
118  .rx_pin = GPIO_PIN(PORT_A, 3),
119  .tx_pin = GPIO_PIN(PORT_A, 2),
120  .rx_af = GPIO_AF7,
121  .tx_af = GPIO_AF7,
122  .bus = APB1,
123  .irqn = USART2_IRQn,
124 #ifdef UART_USE_DMA
125  .dma_stream = 6,
126  .dma_chan = 4
127 #endif
128  },
129  {
130  .dev = USART3,
131  .rcc_mask = RCC_APB1ENR1_USART3EN,
132  .rx_pin = GPIO_PIN(PORT_C, 11),
133  .tx_pin = GPIO_PIN(PORT_C, 10),
134  .rx_af = GPIO_AF7,
135  .tx_af = GPIO_AF7,
136  .bus = APB1,
137  .irqn = USART3_IRQn,
138 #ifdef UART_USE_DMA
139  .dma_stream = 5,
140  .dma_chan = 4
141 #endif
142  },
143  {
144  .dev = USART1,
145  .rcc_mask = RCC_APB2ENR_USART1EN,
146  .rx_pin = GPIO_PIN(PORT_A, 10),
147  .tx_pin = GPIO_PIN(PORT_A, 9),
148  .rx_af = GPIO_AF7,
149  .tx_af = GPIO_AF7,
150  .bus = APB2,
151  .irqn = USART1_IRQn,
152 #ifdef UART_USE_DMA
153  .dma_stream = 4,
154  .dma_chan = 4
155 #endif
156  }
157 };
158 
159 #define UART_0_ISR (isr_usart2)
160 #define UART_1_ISR (isr_usart3)
161 #define UART_2_ISR (isr_usart1)
162 
163 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
164 
170 static const pwm_conf_t pwm_config[] = {
171  {
172  .dev = TIM2,
173  .rcc_mask = RCC_APB1ENR1_TIM2EN,
174  .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
175  { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
176  { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
177  { .pin = GPIO_PIN(PORT_B, 11), .cc_chan = 3} },
178  .af = GPIO_AF1,
179  .bus = APB1
180  },
181  {
182  .dev = TIM3,
183  .rcc_mask = RCC_APB1ENR1_TIM3EN,
184  .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
185  { .pin = GPIO_UNDEF, .cc_chan = 0 },
186  { .pin = GPIO_UNDEF, .cc_chan = 0 },
187  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
188  .af = GPIO_AF2,
189  .bus = APB1
190  },
191  {
192  .dev = TIM8,
193  .rcc_mask = RCC_APB2ENR_TIM8EN,
194  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
195  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
196  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
197  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
198  .af = GPIO_AF3,
199  .bus = APB2
200  }
201 };
202 
203 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
204 
213 static const uint8_t spi_divtable[2][5] = {
214  { /* for APB1 @ 20000000Hz */
215  7, /* -> 78125Hz */
216  5, /* -> 312500Hz */
217  3, /* -> 1250000Hz */
218  1, /* -> 5000000Hz */
219  0 /* -> 10000000Hz */
220  },
221  { /* for APB2 @ 40000000Hz */
222  7, /* -> 156250Hz */
223  6, /* -> 312500Hz */
224  4, /* -> 1250000Hz */
225  2, /* -> 5000000Hz */
226  1 /* -> 10000000Hz */
227  }
228 };
229 
230 static const spi_conf_t spi_config[] = {
231  {
232  .dev = SPI1,
233  .mosi_pin = GPIO_PIN(PORT_A, 7),
234  .miso_pin = GPIO_PIN(PORT_A, 6),
235  .sclk_pin = GPIO_PIN(PORT_A, 5),
236  .cs_pin = GPIO_UNDEF,
237  .af = GPIO_AF5,
238  .rccmask = RCC_APB2ENR_SPI1EN,
239  .apbbus = APB2
240  }
241 };
242 
243 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
244 
250 #define ADC_NUMOF (0)
251 
259 #define RTT_NUMOF (1)
260 #define RTT_FREQUENCY (1024U) /* 32768 / 2^n */
261 #define RTT_MAX_VALUE (0x0000ffff) /* 16-bit timer */
262 
268 #define RTC_NUMOF (1)
269 
271 #ifdef __cplusplus
272 }
273 #endif
274 
275 #endif /* PERIPH_CONF_H */
276 
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 3
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.