boards/nucleo-l476/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Freie Universit├Ąt Berlin
3  * 2017 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 /* 0: no external high speed crystal available
35  * else: actual crystal frequency [in Hz] */
36 #define CLOCK_HSE (0)
37 /* 0: no external low speed crystal available,
38  * 1: external crystal available (always 32.768kHz) */
39 #define CLOCK_LSE (1)
40 /* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */
41 #define CLOCK_CORECLOCK (80000000U)
42 /* PLL configuration: make sure your values are legit!
43  *
44  * compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
45  * with:
46  * PLL_IN: input clock, HSE or MSI @ 48MHz
47  * M: pre-divider, allowed range: [1:8]
48  * N: multiplier, allowed range: [8:86]
49  * R: post-divider, allowed range: [2,4,6,8]
50  *
51  * Also the following constraints need to be met:
52  * (PLL_IN / M) -> [4MHz:16MHz]
53  * (PLL_IN / M) * N -> [64MHz:344MHz]
54  * CORECLOCK -> 80MHz MAX!
55  */
56 #define CLOCK_PLL_M (6)
57 #define CLOCK_PLL_N (20)
58 #define CLOCK_PLL_R (2)
59 /* peripheral clock setup */
60 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
61 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
62 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
63 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
64 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
65 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
66 
72 static const timer_conf_t timer_config[] = {
73  {
74  .dev = TIM5,
75  .max = 0xffffffff,
76  .rcc_mask = RCC_APB1ENR1_TIM5EN,
77  .bus = APB1,
78  .irqn = TIM5_IRQn
79  }
80 };
81 
82 #define TIMER_0_ISR isr_tim5
83 
84 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
85 
91 static const uart_conf_t uart_config[] = {
92  {
93  .dev = USART2,
94  .rcc_mask = RCC_APB1ENR1_USART2EN,
95  .rx_pin = GPIO_PIN(PORT_A, 3),
96  .tx_pin = GPIO_PIN(PORT_A, 2),
97  .rx_af = GPIO_AF7,
98  .tx_af = GPIO_AF7,
99  .bus = APB1,
100  .irqn = USART2_IRQn,
101 #ifdef UART_USE_DMA
102  .dma_stream = 6,
103  .dma_chan = 4
104 #endif
105  },
106  {
107  .dev = USART3,
108  .rcc_mask = RCC_APB1ENR1_USART3EN,
109  .rx_pin = GPIO_PIN(PORT_C, 11),
110  .tx_pin = GPIO_PIN(PORT_C, 10),
111  .rx_af = GPIO_AF7,
112  .tx_af = GPIO_AF7,
113  .bus = APB1,
114  .irqn = USART3_IRQn,
115 #ifdef UART_USE_DMA
116  .dma_stream = 5,
117  .dma_chan = 4
118 #endif
119  },
120  {
121  .dev = USART1,
122  .rcc_mask = RCC_APB2ENR_USART1EN,
123  .rx_pin = GPIO_PIN(PORT_A, 10),
124  .tx_pin = GPIO_PIN(PORT_A, 9),
125  .rx_af = GPIO_AF7,
126  .tx_af = GPIO_AF7,
127  .bus = APB2,
128  .irqn = USART1_IRQn,
129 #ifdef UART_USE_DMA
130  .dma_stream = 4,
131  .dma_chan = 4
132 #endif
133  }
134 };
135 
136 #define UART_0_ISR (isr_usart2)
137 #define UART_1_ISR (isr_usart3)
138 #define UART_2_ISR (isr_usart1)
139 
140 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
141 
147 static const pwm_conf_t pwm_config[] = {
148  {
149  .dev = TIM2,
150  .rcc_mask = RCC_APB1ENR1_TIM2EN,
151  .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
152  { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
153  { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
154  { .pin = GPIO_PIN(PORT_B, 11), .cc_chan = 3} },
155  .af = GPIO_AF1,
156  .bus = APB1
157  },
158  {
159  .dev = TIM3,
160  .rcc_mask = RCC_APB1ENR1_TIM3EN,
161  .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
162  { .pin = GPIO_UNDEF, .cc_chan = 0 },
163  { .pin = GPIO_UNDEF, .cc_chan = 0 },
164  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
165  .af = GPIO_AF2,
166  .bus = APB1
167  },
168  {
169  .dev = TIM8,
170  .rcc_mask = RCC_APB2ENR_TIM8EN,
171  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
172  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
173  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
174  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
175  .af = GPIO_AF3,
176  .bus = APB2
177  }
178 };
179 
180 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
181 
190 static const uint8_t spi_divtable[2][5] = {
191  { /* for APB1 @ 20000000Hz */
192  7, /* -> 78125Hz */
193  5, /* -> 312500Hz */
194  3, /* -> 1250000Hz */
195  1, /* -> 5000000Hz */
196  0 /* -> 10000000Hz */
197  },
198  { /* for APB2 @ 40000000Hz */
199  7, /* -> 156250Hz */
200  6, /* -> 312500Hz */
201  4, /* -> 1250000Hz */
202  2, /* -> 5000000Hz */
203  1 /* -> 10000000Hz */
204  }
205 };
206 
207 static const spi_conf_t spi_config[] = {
208  {
209  .dev = SPI1,
210  .mosi_pin = GPIO_PIN(PORT_A, 7),
211  .miso_pin = GPIO_PIN(PORT_A, 6),
212  .sclk_pin = GPIO_PIN(PORT_A, 5),
213  .cs_pin = GPIO_UNDEF,
214  .af = GPIO_AF0,
215  .rccmask = RCC_APB2ENR_SPI1EN,
216  .apbbus = APB2
217  }
218 };
219 
220 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
221 
227 #define ADC_NUMOF (0)
228 
234 #define DAC_NUMOF (0)
235 
243 #define RTT_NUMOF (1)
244 #define RTT_FREQUENCY (1024U) /* 32768 / 2^n */
245 #define RTT_MAX_VALUE (0x0000ffff) /* 16-bit timer */
246 
248 #ifdef __cplusplus
249 }
250 #endif
251 
252 #endif /* PERIPH_CONF_H */
253 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 3
use alternate function 1
PWM configuration structure.
use alternate function 0
LPC_CTxxBx_Type * dev
PWM device.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.