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periph_conf.h
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1/*
2 * Copyright (C) 2017 Inria
3 * 2017 OTA keys
4 *
5 * This file is subject to the terms and conditions of the GNU Lesser
6 * General Public License v2.1. See the file LICENSE in the top level
7 * directory for more details.
8 */
9
21#ifndef PERIPH_CONF_H
22#define PERIPH_CONF_H
23
24/* Add specific clock configuration (HSE, LSE) for this board here */
25#ifndef CONFIG_BOARD_HAS_LSE
26#define CONFIG_BOARD_HAS_LSE 1
27#endif
28
29#include "periph_cpu.h"
30#include "clk_conf.h"
31#include "cfg_i2c1_pb6_pb7.h"
32#include "cfg_rtt_default.h"
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
43static const uart_conf_t uart_config[] = {
44 {
45 .dev = USART2,
46 .rcc_mask = RCC_APB1ENR1_USART2EN,
47 .rx_pin = GPIO_PIN(PORT_A, 15),
48 .tx_pin = GPIO_PIN(PORT_A, 2),
49 .rx_af = GPIO_AF3,
50 .tx_af = GPIO_AF7,
51 .bus = APB1,
52 .irqn = USART2_IRQn,
53 .type = STM32_USART,
54 .clk_src = 0, /* Use APB clock */
55 },
56 {
57 .dev = USART1,
58 .rcc_mask = RCC_APB2ENR_USART1EN,
59 .rx_pin = GPIO_PIN(PORT_A, 10),
60 .tx_pin = GPIO_PIN(PORT_A, 9),
61 .rx_af = GPIO_AF7,
62 .tx_af = GPIO_AF7,
63 .bus = APB2,
64 .irqn = USART1_IRQn,
65 .type = STM32_USART,
66 .clk_src = 0, /* Use APB clock */
67 },
68};
69
70#define UART_0_ISR (isr_usart2)
71#define UART_1_ISR (isr_usart1)
72
73#define UART_NUMOF ARRAY_SIZE(uart_config)
80static const pwm_conf_t pwm_config[] = {
81 {
82 .dev = TIM1,
83 .rcc_mask = RCC_APB2ENR_TIM1EN,
84 .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 },
85 { .pin = GPIO_UNDEF, .cc_chan = 0 },
86 { .pin = GPIO_UNDEF, .cc_chan = 0 },
87 { .pin = GPIO_UNDEF, .cc_chan = 0 } },
88 .af = GPIO_AF1,
89 .bus = APB2
90 }
91};
92
93#define PWM_NUMOF ARRAY_SIZE(pwm_config)
100static const spi_conf_t spi_config[] = {
101 {
102 .dev = SPI1,
103 .mosi_pin = GPIO_PIN(PORT_B, 5),
104 .miso_pin = GPIO_PIN(PORT_B, 4),
105 .sclk_pin = GPIO_PIN(PORT_B, 3),
106 .cs_pin = SPI_CS_UNDEF,
107 .mosi_af = GPIO_AF5,
108 .miso_af = GPIO_AF5,
109 .sclk_af = GPIO_AF5,
110 .cs_af = GPIO_AF5,
111 .rccmask = RCC_APB2ENR_SPI1EN,
112 .apbbus = APB2
113 }
114};
115
116#define SPI_NUMOF ARRAY_SIZE(spi_config)
119#ifdef __cplusplus
120}
121#endif
122
123#endif /* PERIPH_CONF_H */
@ PORT_B
port B
Definition periph_cpu.h:48
@ PORT_A
port A
Definition periph_cpu.h:47
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Definition periph_cpu.h:46
#define GPIO_UNDEF
Definition of a fitting UNDEF value.
Common configuration for STM32 I2C.
Common configuration for STM32 Timer peripheral based on TIM2, TIM15, and TIM16.
@ GPIO_AF1
use alternate function 1
Definition cpu_gpio.h:103
@ GPIO_AF5
use alternate function 5
Definition cpu_gpio.h:107
@ GPIO_AF3
use alternate function 3
Definition cpu_gpio.h:105
@ GPIO_AF7
use alternate function 7
Definition cpu_gpio.h:109
@ STM32_USART
STM32 USART module type.
Definition cpu_uart.h:38
#define SPI_CS_UNDEF
Define value for unused CS line.
Definition periph_cpu.h:363
@ APB1
Advanced Peripheral Bus 1
Definition periph_cpu.h:79
@ APB2
Advanced Peripheral Bus 2
Definition periph_cpu.h:80
PWM device configuration.
mini_timer_t * dev
Timer used.
SPI device configuration.
Definition periph_cpu.h:337
SPI_t * dev
pointer to the used SPI device
Definition periph_cpu.h:338
UART device configuration.
Definition periph_cpu.h:218
USART_t * dev
pointer to the used UART device
Definition periph_cpu.h:219