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boards/nucleo-l1/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014-2016 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 #define CLOCK_HSI (16000000U) /* frequency of internal oscillator */
34 #define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */
35 /* configuration of PLL prescaler and multiply values */
36 /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
37 #define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
38 #define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
39 /* configuration of peripheral bus clock prescalers */
40 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
41 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
42 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
43 /* configuration of flash access cycles */
44 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
45 
46 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
47 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
48 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
50 
56 #define DAC_NUMOF (0)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM5,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM5EN,
68  .bus = APB1,
69  .irqn = TIM5_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR (isr_tim5)
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 #define RTC_NUMOF (1U)
83 
89 static const uart_conf_t uart_config[] = {
90  {
91  .dev = USART2,
92  .rcc_mask = RCC_APB1ENR_USART2EN,
93  .rx_pin = GPIO_PIN(PORT_A, 3),
94  .tx_pin = GPIO_PIN(PORT_A, 2),
95  .rx_af = GPIO_AF7,
96  .tx_af = GPIO_AF7,
97  .bus = APB1,
98  .irqn = USART2_IRQn
99  },
100  {
101  .dev = USART3,
102  .rcc_mask = RCC_APB1ENR_USART3EN,
103  .rx_pin = GPIO_PIN(PORT_C, 11),
104  .tx_pin = GPIO_PIN(PORT_C, 10),
105  .rx_af = GPIO_AF7,
106  .tx_af = GPIO_AF7,
107  .bus = APB1,
108  .irqn = USART3_IRQn
109  },
110  {
111  .dev = USART1,
112  .rcc_mask = RCC_APB2ENR_USART1EN,
113  .rx_pin = GPIO_PIN(PORT_A, 9),
114  .tx_pin = GPIO_PIN(PORT_A, 10),
115  .rx_af = GPIO_AF7,
116  .tx_af = GPIO_AF7,
117  .bus = APB2,
118  .irqn = USART1_IRQn
119  },
120 };
121 
122 #define UART_0_ISR (isr_usart2)
123 #define UART_1_ISR (isr_usart3)
124 #define UART_2_ISR (isr_usart1)
125 
126 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
127 
133 static const pwm_conf_t pwm_config[] = {
134  {
135  .dev = TIM2,
136  .rcc_mask = RCC_APB1ENR_TIM2EN,
137  .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
138  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
139  { .pin = GPIO_UNDEF, .cc_chan = 0 },
140  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
141  .af = GPIO_AF1,
142  .bus = APB1
143  },
144  {
145  .dev = TIM3,
146  .rcc_mask = RCC_APB1ENR_TIM3EN,
147  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
148  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
149  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
150  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
151  .af = GPIO_AF2,
152  .bus = APB1
153  }
154 };
155 
156 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
157 
166 static const uint8_t spi_divtable[2][5] = {
167  { /* for APB1 @ 32000000Hz */
168  7, /* -> 125000Hz */
169  5, /* -> 500000Hz */
170  4, /* -> 1000000Hz */
171  2, /* -> 4000000Hz */
172  1 /* -> 8000000Hz */
173  },
174  { /* for APB2 @ 32000000Hz */
175  7, /* -> 125000Hz */
176  5, /* -> 500000Hz */
177  4, /* -> 1000000Hz */
178  2, /* -> 4000000Hz */
179  1 /* -> 8000000Hz */
180  }
181 };
182 
183 static const spi_conf_t spi_config[] = {
184  {
185  .dev = SPI1,
186  .mosi_pin = GPIO_PIN(PORT_A, 7),
187  .miso_pin = GPIO_PIN(PORT_A, 6),
188  .sclk_pin = GPIO_PIN(PORT_A, 5),
189  .cs_pin = GPIO_UNDEF,
190  .af = GPIO_AF5,
191  .rccmask = RCC_APB2ENR_SPI1EN,
192  .apbbus = APB2
193  }
194 };
195 
196 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
197 
203 #define I2C_0_EN 1
204 #define I2C_1_EN 1
205 #define I2C_NUMOF (I2C_0_EN + I2C_1_EN)
206 #define I2C_IRQ_PRIO 1
207 #define I2C_APBCLK (36000000U)
208 
209 /* I2C 0 device configuration */
210 #define I2C_0_EVT_ISR isr_i2c1_ev
211 #define I2C_0_ERR_ISR isr_i2c1_er
212 
213 /* I2C 1 device configuration */
214 #define I2C_1_EVT_ISR isr_i2c2_ev
215 #define I2C_1_ERR_ISR isr_i2c2_er
216 
217 static const i2c_conf_t i2c_config[] = {
218  /* device, port, scl-, sda-pin-number, I2C-AF, ER-IRQn, EV-IRQn */
219  {I2C1, GPIO_PIN(PORT_B, 8), GPIO_PIN(PORT_B, 9), GPIO_OD_PU,
220  GPIO_AF4, I2C1_ER_IRQn, I2C1_EV_IRQn},
221  {I2C2, GPIO_PIN(PORT_B, 10), GPIO_PIN(PORT_B, 11), GPIO_OD_PU,
222  GPIO_AF4, I2C2_ER_IRQn, I2C2_EV_IRQn},
223 };
224 
227 #ifdef __cplusplus
228 }
229 #endif
230 
231 #endif /* PERIPH_CONF_H */
232 
use alternate function 4
use alternate function 7
USART_TypeDef * dev
USART device used.
I2C configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.