boards/nucleo-l1/include/periph_conf.h
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1 /*
2  * Copyright (C) 2014-2016 Freie Universit├Ąt Berlin
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
20 #ifndef PERIPH_CONF_H
21 #define PERIPH_CONF_H
22 
23 #include "periph_cpu.h"
24 
25 #ifdef __cplusplus
26 extern "C" {
27 #endif
28 
33 #define CLOCK_HSI (16000000U) /* frequency of internal oscillator */
34 #define CLOCK_CORECLOCK (32000000U) /* targeted core clock frequency */
35 /* configuration of PLL prescaler and multiply values */
36 /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
37 #define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
38 #define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
39 /* configuration of peripheral bus clock prescalers */
40 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
41 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
42 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
43 /* configuration of flash access cycles */
44 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
45 
46 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
47 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
48 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
50 
56 static const timer_conf_t timer_config[] = {
57  {
58  .dev = TIM5,
59  .max = 0xffffffff,
60  .rcc_mask = RCC_APB1ENR_TIM5EN,
61  .bus = APB1,
62  .irqn = TIM5_IRQn
63  }
64 };
65 
66 #define TIMER_0_ISR (isr_tim5)
67 
68 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
69 
75 #define RTC_NUMOF (1U)
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART2,
85  .rcc_mask = RCC_APB1ENR_USART2EN,
86  .rx_pin = GPIO_PIN(PORT_A, 3),
87  .tx_pin = GPIO_PIN(PORT_A, 2),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB1,
91  .irqn = USART2_IRQn
92  },
93  {
94  .dev = USART3,
95  .rcc_mask = RCC_APB1ENR_USART3EN,
96  .rx_pin = GPIO_PIN(PORT_C, 11),
97  .tx_pin = GPIO_PIN(PORT_C, 10),
98  .rx_af = GPIO_AF7,
99  .tx_af = GPIO_AF7,
100  .bus = APB1,
101  .irqn = USART3_IRQn
102  },
103  {
104  .dev = USART1,
105  .rcc_mask = RCC_APB2ENR_USART1EN,
106  .rx_pin = GPIO_PIN(PORT_A, 9),
107  .tx_pin = GPIO_PIN(PORT_A, 10),
108  .rx_af = GPIO_AF7,
109  .tx_af = GPIO_AF7,
110  .bus = APB2,
111  .irqn = USART1_IRQn
112  },
113 };
114 
115 #define UART_0_ISR (isr_usart2)
116 #define UART_1_ISR (isr_usart3)
117 #define UART_2_ISR (isr_usart1)
118 
119 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
120 
126 static const pwm_conf_t pwm_config[] = {
127  {
128  .dev = TIM2,
129  .rcc_mask = RCC_APB1ENR_TIM2EN,
130  .chan = { { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
131  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
132  { .pin = GPIO_UNDEF, .cc_chan = 0 },
133  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
134  .af = GPIO_AF1,
135  .bus = APB1
136  },
137  {
138  .dev = TIM3,
139  .rcc_mask = RCC_APB1ENR_TIM3EN,
140  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
141  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
142  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
143  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
144  .af = GPIO_AF2,
145  .bus = APB1
146  }
147 };
148 
149 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
150 
159 static const uint8_t spi_divtable[2][5] = {
160  { /* for APB1 @ 32000000Hz */
161  7, /* -> 125000Hz */
162  5, /* -> 500000Hz */
163  4, /* -> 1000000Hz */
164  2, /* -> 4000000Hz */
165  1 /* -> 8000000Hz */
166  },
167  { /* for APB2 @ 32000000Hz */
168  7, /* -> 125000Hz */
169  5, /* -> 500000Hz */
170  4, /* -> 1000000Hz */
171  2, /* -> 4000000Hz */
172  1 /* -> 8000000Hz */
173  }
174 };
175 
176 static const spi_conf_t spi_config[] = {
177  {
178  .dev = SPI1,
179  .mosi_pin = GPIO_PIN(PORT_A, 7),
180  .miso_pin = GPIO_PIN(PORT_A, 6),
181  .sclk_pin = GPIO_PIN(PORT_A, 5),
182  .cs_pin = GPIO_UNDEF,
183  .af = GPIO_AF5,
184  .rccmask = RCC_APB2ENR_SPI1EN,
185  .apbbus = APB2
186  }
187 };
188 
189 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
190 
196 #define I2C_0_EN 1
197 #define I2C_1_EN 1
198 #define I2C_NUMOF (I2C_0_EN + I2C_1_EN)
199 #define I2C_IRQ_PRIO 1
200 #define I2C_APBCLK (CLOCK_APB1)
201 
202 /* I2C 0 device configuration */
203 #define I2C_0_EVT_ISR isr_i2c1_ev
204 #define I2C_0_ERR_ISR isr_i2c1_er
205 
206 /* I2C 1 device configuration */
207 #define I2C_1_EVT_ISR isr_i2c2_ev
208 #define I2C_1_ERR_ISR isr_i2c2_er
209 
210 static const i2c_conf_t i2c_config[] = {
211  /* device, port, scl-, sda-pin-number, I2C-AF, ER-IRQn, EV-IRQn */
212  {I2C1, GPIO_PIN(PORT_B, 8), GPIO_PIN(PORT_B, 9), GPIO_OD_PU,
213  GPIO_AF4, I2C1_ER_IRQn, I2C1_EV_IRQn},
214  {I2C2, GPIO_PIN(PORT_B, 10), GPIO_PIN(PORT_B, 11), GPIO_OD_PU,
215  GPIO_AF4, I2C2_ER_IRQn, I2C2_EV_IRQn},
216 };
223 #define ADC_CONFIG { \
224  { GPIO_PIN(PORT_A, 0), 0 }, \
225  { GPIO_PIN(PORT_A, 1), 1 }, \
226  { GPIO_PIN(PORT_A, 4), 4 }, \
227  { GPIO_PIN(PORT_B, 0), 8 }, \
228  { GPIO_PIN(PORT_C, 1), 11 }, \
229  { GPIO_PIN(PORT_C, 0), 10 }, \
230 }
231 
232 #define ADC_NUMOF (6U)
233 
239 #define DAC_CONFIG { \
240  { GPIO_PIN(PORT_A, 4), 1}, \
241  { GPIO_PIN(PORT_A, 5), 2}, \
242 }
243 
244 #define DAC_NUMOF (2U)
245 
247 #ifdef __cplusplus
248 }
249 #endif
250 
251 #endif /* PERIPH_CONF_H */
252 
use alternate function 4
use alternate function 7
USART_TypeDef * dev
USART device used.
I2C configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.