boards/nucleo-l073/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Freie Universit├Ąt Berlin
3  * 2017 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define CLOCK_HSI (16000000U) /* internal oscillator */
35 #define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
36 
37 /* configuration of PLL prescaler and multiply values */
38 /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
39 #define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
40 #define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
41 /* configuration of peripheral bus clock prescalers */
42 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
43 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
44 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
45 /* configuration of flash access cycles */
46 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
47 
48 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
49 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
51 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
52 
58 static const timer_conf_t timer_config[] = {
59  {
60  .dev = TIM2,
61  .max = 0x0000ffff,
62  .rcc_mask = RCC_APB1ENR_TIM2EN,
63  .bus = APB1,
64  .irqn = TIM2_IRQn
65  }
66 };
67 
68 #define TIMER_0_ISR isr_tim2
69 
70 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
71 
77 static const uart_conf_t uart_config[] = {
78  {
79  .dev = USART2,
80  .rcc_mask = RCC_APB1ENR_USART2EN,
81  .rx_pin = GPIO_PIN(PORT_A, 3),
82  .tx_pin = GPIO_PIN(PORT_A, 2),
83  .rx_af = GPIO_AF4,
84  .tx_af = GPIO_AF4,
85  .bus = APB1,
86  .irqn = USART2_IRQn
87  },
88  {
89  .dev = USART1,
90  .rcc_mask = RCC_APB2ENR_USART1EN,
91  .rx_pin = GPIO_PIN(PORT_A, 10),
92  .tx_pin = GPIO_PIN(PORT_A, 9),
93  .rx_af = GPIO_AF4,
94  .tx_af = GPIO_AF4,
95  .bus = APB2,
96  .irqn = USART1_IRQn
97  },
98  {
99  .dev = USART4,
100  .rcc_mask = RCC_APB1ENR_USART4EN,
101  .rx_pin = GPIO_PIN(PORT_C, 11),
102  .tx_pin = GPIO_PIN(PORT_C, 10),
103  .rx_af = GPIO_AF6,
104  .tx_af = GPIO_AF6,
105  .bus = APB1,
106  .irqn = USART4_5_IRQn
107  },
108 };
109 
110 #define UART_0_ISR (isr_usart2)
111 #define UART_1_ISR (isr_usart1)
112 #define UART_2_ISR (isr_usart4_5)
113 
114 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
115 
121 static const pwm_conf_t pwm_config[] = {
122  {
123  .dev = TIM3,
124  .rcc_mask = RCC_APB1ENR_TIM3EN,
125  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
126  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
127  { .pin = GPIO_PIN(PORT_C, 8) , .cc_chan = 2 },
128  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
129  .af = GPIO_AF2,
130  .bus = APB1
131  }
132 };
133 
134 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
135 
144 static const uint8_t spi_divtable[2][5] = {
145  { /* for APB1 @ 32000000Hz */
146  7, /* -> 125000Hz */
147  5, /* -> 500000Hz */
148  4, /* -> 1000000Hz */
149  2, /* -> 4000000Hz */
150  1 /* -> 8000000Hz */
151  },
152  { /* for APB2 @ 32000000Hz */
153  7, /* -> 125000Hz */
154  5, /* -> 500000Hz */
155  4, /* -> 1000000Hz */
156  2, /* -> 4000000Hz */
157  1 /* -> 8000000Hz */
158  }
159 };
160 
161 static const spi_conf_t spi_config[] = {
162  {
163  .dev = SPI1,
164  .mosi_pin = GPIO_PIN(PORT_A, 7),
165  .miso_pin = GPIO_PIN(PORT_A, 6),
166  .sclk_pin = GPIO_PIN(PORT_A, 5),
167  .cs_pin = GPIO_UNDEF,
168  .af = GPIO_AF0,
169  .rccmask = RCC_APB2ENR_SPI1EN,
170  .apbbus = APB2
171  }
172 };
173 
174 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
175 
181 #define ADC_NUMOF (0)
182 
189 #define DAC_NUMOF (0)
190 
196 #define I2C_0_EN 1
197 #define I2C_1_EN 1
198 #define I2C_NUMOF (I2C_0_EN + I2C_1_EN)
199 #define I2C_IRQ_PRIO 1
200 #define I2C_APBCLK (CLOCK_APB1)
201 
202 /* I2C 0 device configuration */
203 #define I2C_0_DEV I2C1
204 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
205 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
206 #define I2C_0_EVT_IRQ I2C1_IRQn
207 #define I2C_0_EVT_ISR isr_i2c1
208 /* I2C 0 pin configuration */
209 #define I2C_0_SCL_PORT PORT_B
210 #define I2C_0_SCL_PIN 8
211 #define I2C_0_SCL_AF 4
212 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_IOPENR_GPIOBEN))
213 #define I2C_0_SDA_PORT PORT_B
214 #define I2C_0_SDA_PIN 9
215 #define I2C_0_SDA_AF 4
216 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_IOPENR_GPIOBEN))
217 
218 /* I2C 1 device configuration */
219 #define I2C_1_DEV I2C3
220 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C3EN))
221 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C3EN))
222 #define I2C_1_EVT_IRQ I2C3_IRQn
223 #define I2C_1_EVT_ISR isr_i2c3
224 /* I2C 1 pin configuration */
225 #define I2C_1_SCL_PORT PORT_A
226 #define I2C_1_SCL_PIN 8
227 #define I2C_1_SCL_AF 3
228 #define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_IOPENR_GPIOAEN))
229 #define I2C_1_SDA_PORT PORT_B
230 #define I2C_1_SDA_PIN 5
231 #define I2C_1_SDA_AF 8
232 #define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_IOPENR_GPIOBEN))
233 
241 #define RTC_NUMOF (1U)
242 
244 #ifdef __cplusplus
245 }
246 #endif
247 
248 #endif /* PERIPH_CONF_H */
249 
use alternate function 4
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 6
PWM configuration structure.
use alternate function 0
LPC_CTxxBx_Type * dev
PWM device.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.