boards/nucleo-l073/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Freie Universit├Ąt Berlin
3  * 2017 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
23 #ifndef PERIPH_CONF_H
24 #define PERIPH_CONF_H
25 
26 #include "periph_cpu.h"
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
36 #define CLOCK_HSI (16000000U) /* internal oscillator */
37 #define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
38 
39 /* configuration of PLL prescaler and multiply values */
40 /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
41 #define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
42 #define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
43 /* configuration of peripheral bus clock prescalers */
44 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
45 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
46 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
47 /* configuration of flash access cycles */
48 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
49 
50 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
51 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
53 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
54 
60 static const timer_conf_t timer_config[] = {
61  {
62  .dev = TIM2,
63  .max = 0x0000ffff,
64  .rcc_mask = RCC_APB1ENR_TIM2EN,
65  .bus = APB1,
66  .irqn = TIM2_IRQn
67  }
68 };
69 
70 #define TIMER_0_ISR isr_tim2
71 
72 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
73 
79 static const uart_conf_t uart_config[] = {
80  {
81  .dev = USART2,
82  .rcc_mask = RCC_APB1ENR_USART2EN,
83  .rx_pin = GPIO_PIN(PORT_A, 3),
84  .tx_pin = GPIO_PIN(PORT_A, 2),
85  .rx_af = GPIO_AF4,
86  .tx_af = GPIO_AF4,
87  .bus = APB1,
88  .irqn = USART2_IRQn
89  },
90  {
91  .dev = USART1,
92  .rcc_mask = RCC_APB2ENR_USART1EN,
93  .rx_pin = GPIO_PIN(PORT_A, 10),
94  .tx_pin = GPIO_PIN(PORT_A, 9),
95  .rx_af = GPIO_AF4,
96  .tx_af = GPIO_AF4,
97  .bus = APB2,
98  .irqn = USART1_IRQn
99  },
100  {
101  .dev = USART4,
102  .rcc_mask = RCC_APB1ENR_USART4EN,
103  .rx_pin = GPIO_PIN(PORT_C, 11),
104  .tx_pin = GPIO_PIN(PORT_C, 10),
105  .rx_af = GPIO_AF6,
106  .tx_af = GPIO_AF6,
107  .bus = APB1,
108  .irqn = USART4_5_IRQn
109  },
110 };
111 
112 #define UART_0_ISR (isr_usart2)
113 #define UART_1_ISR (isr_usart1)
114 #define UART_2_ISR (isr_usart4_5)
115 
116 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
117 
123 static const pwm_conf_t pwm_config[] = {
124  {
125  .dev = TIM3,
126  .rcc_mask = RCC_APB1ENR_TIM3EN,
127  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
128  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
129  { .pin = GPIO_PIN(PORT_C, 8) , .cc_chan = 2 },
130  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
131  .af = GPIO_AF2,
132  .bus = APB1
133  }
134 };
135 
136 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
137 
146 static const uint8_t spi_divtable[2][5] = {
147  { /* for APB1 @ 32000000Hz */
148  7, /* -> 125000Hz */
149  5, /* -> 500000Hz */
150  4, /* -> 1000000Hz */
151  2, /* -> 4000000Hz */
152  1 /* -> 8000000Hz */
153  },
154  { /* for APB2 @ 32000000Hz */
155  7, /* -> 125000Hz */
156  5, /* -> 500000Hz */
157  4, /* -> 1000000Hz */
158  2, /* -> 4000000Hz */
159  1 /* -> 8000000Hz */
160  }
161 };
162 
163 static const spi_conf_t spi_config[] = {
164  {
165  .dev = SPI1,
166  .mosi_pin = GPIO_PIN(PORT_A, 7),
167  .miso_pin = GPIO_PIN(PORT_A, 6),
168  .sclk_pin = GPIO_PIN(PORT_A, 5),
169  .cs_pin = GPIO_UNDEF,
170  .af = GPIO_AF0,
171  .rccmask = RCC_APB2ENR_SPI1EN,
172  .apbbus = APB2
173  }
174 };
175 
176 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
177 
183 #define ADC_CONFIG { \
184  { GPIO_PIN(PORT_A, 0), 0 }, \
185  { GPIO_PIN(PORT_A, 1), 1 }, \
186  { GPIO_PIN(PORT_A, 4), 4 }, \
187  { GPIO_PIN(PORT_B, 0), 8 }, \
188  { GPIO_PIN(PORT_C, 1), 11 },\
189  { GPIO_PIN(PORT_C, 0), 10 } \
190 }
191 
192 #define ADC_NUMOF (6U)
193 
199 #define I2C_0_EN 1
200 #define I2C_1_EN 1
201 #define I2C_NUMOF (I2C_0_EN + I2C_1_EN)
202 #define I2C_IRQ_PRIO 1
203 #define I2C_APBCLK (CLOCK_APB1)
204 
205 /* I2C 0 device configuration */
206 #define I2C_0_DEV I2C1
207 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
208 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
209 #define I2C_0_EVT_IRQ I2C1_IRQn
210 #define I2C_0_EVT_ISR isr_i2c1
211 /* I2C 0 pin configuration */
212 #define I2C_0_SCL_PORT PORT_B
213 #define I2C_0_SCL_PIN 8
214 #define I2C_0_SCL_AF 4
215 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB, RCC_IOPENR_GPIOBEN))
216 #define I2C_0_SDA_PORT PORT_B
217 #define I2C_0_SDA_PIN 9
218 #define I2C_0_SDA_AF 4
219 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB, RCC_IOPENR_GPIOBEN))
220 
221 /* I2C 1 device configuration */
222 #define I2C_1_DEV I2C2
223 #define I2C_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C2EN))
224 #define I2C_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C2EN))
225 #define I2C_1_EVT_IRQ I2C2_IRQn
226 #define I2C_1_EVT_ISR isr_i2c2
227 /* I2C 1 pin configuration */
228 #define I2C_1_SCL_PORT PORT_B
229 #define I2C_1_SCL_PIN 13
230 #define I2C_1_SCL_AF 5
231 #define I2C_1_SCL_CLKEN() (periph_clk_en(AHB, RCC_IOPENR_GPIOBEN))
232 #define I2C_1_SDA_PORT PORT_B
233 #define I2C_1_SDA_PIN 14
234 #define I2C_1_SDA_AF 5
235 #define I2C_1_SDA_CLKEN() (periph_clk_en(AHB, RCC_IOPENR_GPIOBEN))
236 
243 #define RTC_NUMOF (1U)
244 
246 #ifdef __cplusplus
247 }
248 #endif
249 
250 #endif /* PERIPH_CONF_H */
251 
use alternate function 4
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
use alternate function 6
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 0
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.