boards/nucleo-l053/include/periph_conf.h
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1 /*
2  * Copyright (C) 2017 Freie Universit├Ąt Berlin
3  * 2017 Inria
4  *
5  * This file is subject to the terms and conditions of the GNU Lesser
6  * General Public License v2.1. See the file LICENSE in the top level
7  * directory for more details.
8  */
9 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
34 #define CLOCK_HSI (16000000U) /* internal oscillator */
35 #define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */
36 
37 /* configuration of PLL prescaler and multiply values */
38 /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */
39 #define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2
40 #define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4
41 /* configuration of peripheral bus clock prescalers */
42 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */
43 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */
44 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */
45 /* configuration of flash access cycles */
46 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY
47 
48 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
49 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
51 #define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
52 
58 static const timer_conf_t timer_config[] = {
59  {
60  .dev = TIM2,
61  .max = 0x0000ffff,
62  .rcc_mask = RCC_APB1ENR_TIM2EN,
63  .bus = APB1,
64  .irqn = TIM2_IRQn
65  }
66 };
67 
68 #define TIMER_0_ISR isr_tim2
69 
70 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
71 
77 static const uart_conf_t uart_config[] = {
78  {
79  .dev = USART2,
80  .rcc_mask = RCC_APB1ENR_USART2EN,
81  .rx_pin = GPIO_PIN(PORT_A, 3),
82  .tx_pin = GPIO_PIN(PORT_A, 2),
83  .rx_af = GPIO_AF4,
84  .tx_af = GPIO_AF4,
85  .bus = APB1,
86  .irqn = USART2_IRQn
87  },
88  {
89  .dev = USART1,
90  .rcc_mask = RCC_APB2ENR_USART1EN,
91  .rx_pin = GPIO_PIN(PORT_A, 10),
92  .tx_pin = GPIO_PIN(PORT_A, 9),
93  .rx_af = GPIO_AF4,
94  .tx_af = GPIO_AF4,
95  .bus = APB2,
96  .irqn = USART1_IRQn
97  }
98 };
99 
100 #define UART_0_ISR (isr_usart2)
101 #define UART_1_ISR (isr_usart1)
102 
103 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
104 
110 static const pwm_conf_t pwm_config[] = {
111  {
112  .dev = TIM22,
113  .rcc_mask = RCC_APB2ENR_TIM22EN,
114  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
115  { .pin = GPIO_PIN(PORT_B, 5), .cc_chan = 1 },
116  { .pin = GPIO_UNDEF, .cc_chan = 0 },
117  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
118  .af = GPIO_AF4,
119  .bus = APB2
120  }
121 };
122 
123 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
124 
133 static const uint8_t spi_divtable[2][5] = {
134  { /* for APB1 @ 32000000Hz */
135  7, /* -> 125000Hz */
136  5, /* -> 500000Hz */
137  4, /* -> 1000000Hz */
138  2, /* -> 4000000Hz */
139  1 /* -> 8000000Hz */
140  },
141  { /* for APB2 @ 32000000Hz */
142  7, /* -> 125000Hz */
143  5, /* -> 500000Hz */
144  4, /* -> 1000000Hz */
145  2, /* -> 4000000Hz */
146  1 /* -> 8000000Hz */
147  }
148 };
149 
150 static const spi_conf_t spi_config[] = {
151  {
152  .dev = SPI1,
153  .mosi_pin = GPIO_PIN(PORT_A, 7),
154  .miso_pin = GPIO_PIN(PORT_A, 6),
155  .sclk_pin = GPIO_PIN(PORT_A, 5),
156  .cs_pin = GPIO_UNDEF,
157  .af = GPIO_AF0,
158  .rccmask = RCC_APB2ENR_SPI1EN,
159  .apbbus = APB2
160  }
161 };
162 
163 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
164 
170 #define ADC_NUMOF (0)
171 
177 #define RTC_NUMOF (1U)
178 
180 #ifdef __cplusplus
181 }
182 #endif
183 
184 #endif /* PERIPH_CONF_H */
185 
use alternate function 4
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
PWM configuration structure.
use alternate function 0
LPC_CTxxBx_Type * dev
PWM device.
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.