boards/nucleo-f446/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 180MHz */
39 #define CLOCK_CORECLOCK (180000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (8000000U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (1)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
53 
54 /* Main PLL factors */
55 #define CLOCK_PLL_M (4)
56 #define CLOCK_PLL_N (180)
57 #define CLOCK_PLL_P (2)
58 #define CLOCK_PLL_Q (0)
59 
60 /* PLL SAI configuration */
61 #define CLOCK_ENABLE_PLL_SAI (1)
62 #define CLOCK_PLL_SAI_M (4)
63 #define CLOCK_PLL_SAI_N (192)
64 #define CLOCK_PLL_SAI_P (8)
65 #define CLOCK_PLL_SAI_Q (0)
66 
67 /* Use alternative source for 48MHz clock */
68 #define CLOCK_USE_ALT_48MHZ (1)
69 
75 static const timer_conf_t timer_config[] = {
76  {
77  .dev = TIM5,
78  .max = 0xffffffff,
79  .rcc_mask = RCC_APB1ENR_TIM5EN,
80  .bus = APB1,
81  .irqn = TIM5_IRQn
82  }
83 };
84 
85 #define TIMER_0_ISR isr_tim5
86 
87 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
88 
94 static const uart_conf_t uart_config[] = {
95  {
96  .dev = USART2,
97  .rcc_mask = RCC_APB1ENR_USART2EN,
98  .rx_pin = GPIO_PIN(PORT_A, 3),
99  .tx_pin = GPIO_PIN(PORT_A, 2),
100  .rx_af = GPIO_AF7,
101  .tx_af = GPIO_AF7,
102  .bus = APB1,
103  .irqn = USART2_IRQn,
104 #ifdef UART_USE_DMA
105  .dma_stream = 6,
106  .dma_chan = 4
107 #endif
108  },
109  {
110  .dev = USART3,
111  .rcc_mask = RCC_APB1ENR_USART3EN,
112  .rx_pin = GPIO_PIN(PORT_C, 11),
113  .tx_pin = GPIO_PIN(PORT_C, 10),
114  .rx_af = GPIO_AF7,
115  .tx_af = GPIO_AF7,
116  .bus = APB1,
117  .irqn = USART3_IRQn,
118 #ifdef UART_USE_DMA
119  .dma_stream = 5,
120  .dma_chan = 4
121 #endif
122  },
123  {
124  .dev = USART1,
125  .rcc_mask = RCC_APB2ENR_USART1EN,
126  .rx_pin = GPIO_PIN(PORT_A, 10),
127  .tx_pin = GPIO_PIN(PORT_A, 9),
128  .rx_af = GPIO_AF7,
129  .tx_af = GPIO_AF7,
130  .bus = APB2,
131  .irqn = USART1_IRQn,
132 #ifdef UART_USE_DMA
133  .dma_stream = 4,
134  .dma_chan = 4
135 #endif
136  },
137 };
138 
139 #define UART_0_ISR (isr_usart2)
140 #define UART_0_DMA_ISR (isr_dma1_stream6)
141 #define UART_1_ISR (isr_usart3)
142 #define UART_1_DMA_ISR (isr_dma1_stream5)
143 #define UART_2_ISR (isr_usart1)
144 #define UART_2_DMA_ISR (isr_dma1_stream4)
145 
146 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
147 
153 static const pwm_conf_t pwm_config[] = {
154  {
155  .dev = TIM2,
156  .rcc_mask = RCC_APB1ENR_TIM2EN,
157  .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
158  { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
159  { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
160  { .pin = GPIO_PIN(PORT_B, 2), .cc_chan = 3} },
161  .af = GPIO_AF1,
162  .bus = APB1
163  },
164  {
165  .dev = TIM8,
166  .rcc_mask = RCC_APB2ENR_TIM8EN,
167  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
168  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
169  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
170  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
171  .af = GPIO_AF3,
172  .bus = APB2
173  },
174 };
175 
176 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
177 
183 static const qdec_conf_t qdec_config[] = {
184  {
185  .dev = TIM3,
186  .max = 0xffffffff,
187  .rcc_mask = RCC_APB1ENR_TIM3EN,
188  .chan = { { .pin = GPIO_PIN(PORT_A, 6), .cc_chan = 0 },
189  { .pin = GPIO_PIN(PORT_A, 7), .cc_chan = 1 } },
190  .af = GPIO_AF2,
191  .bus = APB1,
192  .irqn = TIM3_IRQn
193  },
194  {
195  .dev = TIM4,
196  .max = 0xffffffff,
197  .rcc_mask = RCC_APB1ENR_TIM4EN,
198  .chan = { { .pin = GPIO_PIN(PORT_B, 6), .cc_chan = 0 },
199  { .pin = GPIO_PIN(PORT_B, 7), .cc_chan = 1 } },
200  .af = GPIO_AF2,
201  .bus = APB1,
202  .irqn = TIM4_IRQn
203  },
204 };
205 
206 #define QDEC_0_ISR isr_tim3
207 #define QDEC_1_ISR isr_tim4
208 
209 #define QDEC_NUMOF (sizeof(qdec_config) / sizeof(qdec_config[0]))
210 
219 static const uint8_t spi_divtable[2][5] = {
220  { /* for APB1 @ 90000000Hz */
221  7, /* -> 351562Hz */
222  7, /* -> 351562Hz */
223  6, /* -> 703125Hz */
224  3, /* -> 5625000Hz */
225  2 /* -> 11250000Hz */
226  },
227  { /* for APB2 @ 180000000Hz */
228  7, /* -> 703125Hz */
229  7, /* -> 703125Hz */
230  7, /* -> 703125Hz */
231  4, /* -> 5625000Hz */
232  3 /* -> 11250000Hz */
233  }
234 };
235 
236 static const spi_conf_t spi_config[] = {
237  {
238  .dev = SPI1,
239  .mosi_pin = GPIO_PIN(PORT_A, 7),
240  .miso_pin = GPIO_PIN(PORT_A, 6),
241  .sclk_pin = GPIO_PIN(PORT_A, 5),
242  .cs_pin = GPIO_PIN(PORT_A, 4),
243  .af = GPIO_AF5,
244  .rccmask = RCC_APB2ENR_SPI1EN,
245  .apbbus = APB2
246  },
247  {
248  .dev = SPI2,
249  .mosi_pin = GPIO_PIN(PORT_B, 15),
250  .miso_pin = GPIO_PIN(PORT_B, 14),
251  .sclk_pin = GPIO_PIN(PORT_B, 13),
252  .cs_pin = GPIO_PIN(PORT_B, 12),
253  .af = GPIO_AF5,
254  .rccmask = RCC_APB1ENR_SPI2EN,
255  .apbbus = APB1
256  },
257  {
258  .dev = SPI3,
259  .mosi_pin = GPIO_PIN(PORT_C, 12),
260  .miso_pin = GPIO_PIN(PORT_C, 11),
261  .sclk_pin = GPIO_PIN(PORT_C, 10),
262  .cs_pin = GPIO_UNDEF,
263  .af = GPIO_AF6,
264  .rccmask = RCC_APB1ENR_SPI3EN,
265  .apbbus = APB1
266  }
267 };
268 
269 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
270 
277 #define I2C_NUMOF (1U)
278 #define I2C_0_EN 1
279 #define I2C_IRQ_PRIO 1
280 #define I2C_APBCLK (CLOCK_APB1)
281 
282 /* I2C 0 device configuration */
283 #define I2C_0_DEV I2C1
284 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
285 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
286 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
287 #define I2C_0_EVT_ISR isr_i2c1_ev
288 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
289 #define I2C_0_ERR_ISR isr_i2c1_er
290 /* I2C 0 pin configuration */
291 #define I2C_0_SCL_PORT GPIOB
292 #define I2C_0_SCL_PIN 8
293 #define I2C_0_SCL_AF 4
294 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
295 #define I2C_0_SDA_PORT GPIOB
296 #define I2C_0_SDA_PIN 9
297 #define I2C_0_SDA_AF 4
298 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
299 
311 #define ADC_NUMOF (6U)
312 #define ADC_CONFIG { \
313  {GPIO_PIN(PORT_A, 0), 0, 0}, \
314  {GPIO_PIN(PORT_A, 1), 0, 1}, \
315  {GPIO_PIN(PORT_A, 4), 0, 4}, \
316  {GPIO_PIN(PORT_B, 0), 0, 8}, \
317  {GPIO_PIN(PORT_C, 1), 0, 11}, \
318  {GPIO_PIN(PORT_C, 0), 0, 10}, \
319 }
320 
322 #ifdef __cplusplus
323 }
324 #endif
325 
326 #endif /* PERIPH_CONF_H */
327 
use alternate function 7
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
use alternate function 6
TIM_TypeDef * dev
Timer used.
use alternate function 3
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.