boards/nucleo-f446/include/periph_conf.h
Go to the documentation of this file.
1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 180MHz */
37 #define CLOCK_CORECLOCK (180000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (8000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (1)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
49 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
51 
52 /* Main PLL factors */
53 #define CLOCK_PLL_M (4)
54 #define CLOCK_PLL_N (180)
55 #define CLOCK_PLL_P (2)
56 #define CLOCK_PLL_Q (0)
57 
58 /* PLL SAI configuration */
59 #define CLOCK_ENABLE_PLL_SAI (1)
60 #define CLOCK_PLL_SAI_M (4)
61 #define CLOCK_PLL_SAI_N (192)
62 #define CLOCK_PLL_SAI_P (8)
63 #define CLOCK_PLL_SAI_Q (0)
64 
65 /* Use alternative source for 48MHz clock */
66 #define CLOCK_USE_ALT_48MHZ (1)
67 
73 static const timer_conf_t timer_config[] = {
74  {
75  .dev = TIM5,
76  .max = 0xffffffff,
77  .rcc_mask = RCC_APB1ENR_TIM5EN,
78  .bus = APB1,
79  .irqn = TIM5_IRQn
80  }
81 };
82 
83 #define TIMER_0_ISR isr_tim5
84 
85 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
86 
92 static const uart_conf_t uart_config[] = {
93  {
94  .dev = USART2,
95  .rcc_mask = RCC_APB1ENR_USART2EN,
96  .rx_pin = GPIO_PIN(PORT_A, 3),
97  .tx_pin = GPIO_PIN(PORT_A, 2),
98  .rx_af = GPIO_AF7,
99  .tx_af = GPIO_AF7,
100  .bus = APB1,
101  .irqn = USART2_IRQn,
102 #ifdef UART_USE_DMA
103  .dma_stream = 6,
104  .dma_chan = 4
105 #endif
106  },
107  {
108  .dev = USART3,
109  .rcc_mask = RCC_APB1ENR_USART3EN,
110  .rx_pin = GPIO_PIN(PORT_C, 11),
111  .tx_pin = GPIO_PIN(PORT_C, 10),
112  .rx_af = GPIO_AF7,
113  .tx_af = GPIO_AF7,
114  .bus = APB1,
115  .irqn = USART3_IRQn,
116 #ifdef UART_USE_DMA
117  .dma_stream = 5,
118  .dma_chan = 4
119 #endif
120  },
121  {
122  .dev = USART1,
123  .rcc_mask = RCC_APB2ENR_USART1EN,
124  .rx_pin = GPIO_PIN(PORT_A, 10),
125  .tx_pin = GPIO_PIN(PORT_A, 9),
126  .rx_af = GPIO_AF7,
127  .tx_af = GPIO_AF7,
128  .bus = APB2,
129  .irqn = USART1_IRQn,
130 #ifdef UART_USE_DMA
131  .dma_stream = 4,
132  .dma_chan = 4
133 #endif
134  },
135 };
136 
137 #define UART_0_ISR (isr_usart2)
138 #define UART_0_DMA_ISR (isr_dma1_stream6)
139 #define UART_1_ISR (isr_usart3)
140 #define UART_1_DMA_ISR (isr_dma1_stream5)
141 #define UART_2_ISR (isr_usart1)
142 #define UART_2_DMA_ISR (isr_dma1_stream4)
143 
144 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
145 
151 static const pwm_conf_t pwm_config[] = {
152  {
153  .dev = TIM2,
154  .rcc_mask = RCC_APB1ENR_TIM2EN,
155  .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
156  { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
157  { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
158  { .pin = GPIO_PIN(PORT_B, 2), .cc_chan = 3} },
159  .af = GPIO_AF1,
160  .bus = APB1
161  },
162  {
163  .dev = TIM3,
164  .rcc_mask = RCC_APB1ENR_TIM3EN,
165  .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
166  { .pin = GPIO_UNDEF, .cc_chan = 0 },
167  { .pin = GPIO_UNDEF, .cc_chan = 0 },
168  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
169  .af = GPIO_AF2,
170  .bus = APB1
171  },
172  {
173  .dev = TIM8,
174  .rcc_mask = RCC_APB2ENR_TIM8EN,
175  .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
176  { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
177  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
178  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
179  .af = GPIO_AF3,
180  .bus = APB2
181  },
182 };
183 
184 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
185 
194 static const uint8_t spi_divtable[2][5] = {
195  { /* for APB1 @ 90000000Hz */
196  7, /* -> 351562Hz */
197  7, /* -> 351562Hz */
198  6, /* -> 703125Hz */
199  3, /* -> 5625000Hz */
200  2 /* -> 11250000Hz */
201  },
202  { /* for APB2 @ 180000000Hz */
203  7, /* -> 703125Hz */
204  7, /* -> 703125Hz */
205  7, /* -> 703125Hz */
206  4, /* -> 5625000Hz */
207  3 /* -> 11250000Hz */
208  }
209 };
210 
211 static const spi_conf_t spi_config[] = {
212  {
213  .dev = SPI1,
214  .mosi_pin = GPIO_PIN(PORT_A, 7),
215  .miso_pin = GPIO_PIN(PORT_A, 6),
216  .sclk_pin = GPIO_PIN(PORT_A, 5),
217  .cs_pin = GPIO_PIN(PORT_A, 4),
218  .af = GPIO_AF5,
219  .rccmask = RCC_APB2ENR_SPI1EN,
220  .apbbus = APB2
221  },
222  {
223  .dev = SPI2,
224  .mosi_pin = GPIO_PIN(PORT_B, 15),
225  .miso_pin = GPIO_PIN(PORT_B, 14),
226  .sclk_pin = GPIO_PIN(PORT_B, 13),
227  .cs_pin = GPIO_PIN(PORT_B, 12),
228  .af = GPIO_AF5,
229  .rccmask = RCC_APB1ENR_SPI2EN,
230  .apbbus = APB1
231  },
232  {
233  .dev = SPI3,
234  .mosi_pin = GPIO_PIN(PORT_C, 12),
235  .miso_pin = GPIO_PIN(PORT_C, 11),
236  .sclk_pin = GPIO_PIN(PORT_C, 10),
237  .cs_pin = GPIO_UNDEF,
238  .af = GPIO_AF6,
239  .rccmask = RCC_APB1ENR_SPI3EN,
240  .apbbus = APB1
241  }
242 };
243 
244 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
245 
252 #define I2C_NUMOF (1U)
253 #define I2C_0_EN 1
254 #define I2C_IRQ_PRIO 1
255 #define I2C_APBCLK (CLOCK_APB1)
256 
257 /* I2C 0 device configuration */
258 #define I2C_0_DEV I2C1
259 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
260 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
261 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
262 #define I2C_0_EVT_ISR isr_i2c1_ev
263 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
264 #define I2C_0_ERR_ISR isr_i2c1_er
265 /* I2C 0 pin configuration */
266 #define I2C_0_SCL_PORT GPIOB
267 #define I2C_0_SCL_PIN 8
268 #define I2C_0_SCL_AF 4
269 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
270 #define I2C_0_SDA_PORT GPIOB
271 #define I2C_0_SDA_PIN 9
272 #define I2C_0_SDA_AF 4
273 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
274 
286 #define ADC_NUMOF (6U)
287 #define ADC_CONFIG { \
288  {GPIO_PIN(PORT_A, 0), 0, 0}, \
289  {GPIO_PIN(PORT_A, 1), 0, 1}, \
290  {GPIO_PIN(PORT_A, 4), 0, 4}, \
291  {GPIO_PIN(PORT_B, 0), 0, 8}, \
292  {GPIO_PIN(PORT_C, 1), 0, 11}, \
293  {GPIO_PIN(PORT_C, 0), 0, 10}, \
294 }
295 
297 #ifdef __cplusplus
298 }
299 #endif
300 
301 #endif /* PERIPH_CONF_H */
302 
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 6
use alternate function 3
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.