boards/nucleo-f411/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 100MHz */
37 #define CLOCK_CORECLOCK (96000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (8000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (1)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
49 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
51 
52 /* Main PLL factors */
53 #define CLOCK_PLL_M (4)
54 #define CLOCK_PLL_N (192)
55 #define CLOCK_PLL_P (4)
56 #define CLOCK_PLL_Q (8)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM5,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM5EN,
68  .bus = APB1,
69  .irqn = TIM5_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim5
74 #define TIMER_1_ISR isr_tim4
75 
76 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
77 
83 static const uart_conf_t uart_config[] = {
84  {
85  .dev = USART2,
86  .rcc_mask = RCC_APB1ENR_USART2EN,
87  .rx_pin = GPIO_PIN(PORT_A,3),
88  .tx_pin = GPIO_PIN(PORT_A,2),
89  .rx_af = GPIO_AF7,
90  .tx_af = GPIO_AF7,
91  .bus = APB1,
92  .irqn = USART2_IRQn,
93 #ifdef UART_USE_DMA
94  .dma_stream = 6,
95  .dma_chan = 4
96 #endif
97  },
98  {
99  .dev = USART1,
100  .rcc_mask = RCC_APB2ENR_USART1EN,
101  .rx_pin = GPIO_PIN(PORT_A, 10),
102  .tx_pin = GPIO_PIN(PORT_A, 9),
103  .rx_af = GPIO_AF7,
104  .tx_af = GPIO_AF7,
105  .bus = APB2,
106  .irqn = USART1_IRQn,
107 #ifdef UART_USE_DMA
108  .dma_stream = 6,
109  .dma_chan = 3
110 #endif
111  },
112  {
113  .dev = USART6,
114  .rcc_mask = RCC_APB2ENR_USART6EN,
115  .rx_pin = GPIO_PIN(PORT_A, 12),
116  .tx_pin = GPIO_PIN(PORT_A, 11),
117  .rx_af = GPIO_AF8,
118  .tx_af = GPIO_AF8,
119  .bus = APB2,
120  .irqn = USART6_IRQn,
121 #ifdef UART_USE_DMA
122  .dma_stream = 6,
123  .dma_chan = 2
124 #endif
125  }
126 };
127 
128 /* assign ISR vector names */
129 #define UART_0_ISR isr_usart2
130 #define UART_0_DMA_ISR isr_dma1_stream6
131 #define UART_1_ISR isr_usart1
132 #define UART_1_DMA_ISR isr_dma1_stream6
133 #define UART_2_ISR isr_usart6
134 #define UART_2_DMA_ISR isr_dma1_stream6
135 
136 /* deduct number of defined UART interfaces */
137 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
138 
143 static const pwm_conf_t pwm_config[] = {
144  {
145  .dev = TIM2,
146  .rcc_mask = RCC_APB1ENR_TIM2EN,
147  .chan = { { .pin = GPIO_PIN(PORT_A, 15) , .cc_chan = 0 },
148  { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
149  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
150  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
151  .af = GPIO_AF1,
152  .bus = APB1
153  },
154  {
155  .dev = TIM3,
156  .rcc_mask = RCC_APB1ENR_TIM3EN,
157  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
158  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
159  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
160  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
161  .af = GPIO_AF2,
162  .bus = APB1
163  },
164 };
165 
166 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
167 
176 static const uint8_t spi_divtable[2][5] = {
177  { /* for APB1 @ 48000000Hz */
178  7, /* -> 187500Hz */
179  6, /* -> 375000Hz */
180  5, /* -> 750000Hz */
181  2, /* -> 6000000Hz */
182  1 /* -> 12000000Hz */
183  },
184  { /* for APB2 @ 96000000Hz */
185  7, /* -> 375000Hz */
186  7, /* -> 375000Hz */
187  6, /* -> 750000Hz */
188  3, /* -> 6000000Hz */
189  2 /* -> 12000000Hz */
190  }
191 };
192 
193 static const spi_conf_t spi_config[] = {
194  {
195  .dev = SPI1,
196  .mosi_pin = GPIO_PIN(PORT_A, 7),
197  .miso_pin = GPIO_PIN(PORT_A, 6),
198  .sclk_pin = GPIO_PIN(PORT_A, 5),
199  .cs_pin = GPIO_PIN(PORT_A, 4),
200  .af = GPIO_AF5,
201  .rccmask = RCC_APB2ENR_SPI1EN,
202  .apbbus = APB2
203  }
204 };
205 
206 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
207 
213 #define I2C_NUMOF (1U)
214 #define I2C_0_EN 1
215 #define I2C_IRQ_PRIO 1
216 #define I2C_APBCLK (CLOCK_APB1)
217 
218 /* I2C 0 device configuration */
219 #define I2C_0_DEV I2C1
220 #define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
221 #define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
222 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
223 #define I2C_0_EVT_ISR isr_i2c1_ev
224 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
225 #define I2C_0_ERR_ISR isr_i2c1_er
226 /* I2C 0 pin configuration */
227 #define I2C_0_SCL_PORT GPIOB
228 #define I2C_0_SCL_PIN 8
229 #define I2C_0_SCL_AF 4
230 #define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
231 #define I2C_0_SDA_PORT GPIOB
232 #define I2C_0_SDA_PIN 9
233 #define I2C_0_SDA_AF 4
234 #define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
235 
247 #define ADC_NUMOF (6U)
248 #define ADC_CONFIG { \
249  {GPIO_PIN(PORT_A, 0), 0, 0}, \
250  {GPIO_PIN(PORT_A, 1), 0, 1}, \
251  {GPIO_PIN(PORT_A, 4), 0, 4}, \
252  {GPIO_PIN(PORT_B, 0), 0, 8}, \
253  {GPIO_PIN(PORT_C, 1), 0, 11}, \
254  {GPIO_PIN(PORT_C, 0), 0, 10}, \
255 }
256 
258 #ifdef __cplusplus
259 }
260 #endif
261 
262 #endif /* PERIPH_CONF_H */
263 
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.