boards/nucleo-f411/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H_
20 #define PERIPH_CONF_H_
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLOCK_HSE (8000000U) /* external oscillator */
33 #define CLOCK_CORECLOCK (100000000U) /* desired core clock frequency */
34 
35 /* the actual PLL values are automatically generated */
36 #define CLOCK_PLL_M (CLOCK_HSE / 1000000)
37 #define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
38 #define CLOCK_PLL_P (2U)
39 #define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
40 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
41 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
42 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
43 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
44 
45 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
48 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
49 
55 static const timer_conf_t timer_config[] = {
56  {
57  .dev = TIM5,
58  .max = 0xffffffff,
59  .rcc_mask = RCC_APB1ENR_TIM5EN,
60  .bus = APB1,
61  .irqn = TIM5_IRQn
62  }
63 };
64 
65 #define TIMER_0_ISR isr_tim5
66 #define TIMER_1_ISR isr_tim4
67 
68 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
69 
75 static const uart_conf_t uart_config[] = {
76  {
77  .dev = USART2,
78  .rcc_mask = RCC_APB1ENR_USART2EN,
79  .rx_pin = GPIO_PIN(PORT_A,3),
80  .tx_pin = GPIO_PIN(PORT_A,2),
81  .rx_af = GPIO_AF7,
82  .tx_af = GPIO_AF7,
83  .bus = APB1,
84  .irqn = USART2_IRQn,
85 #ifdef UART_USE_DMA
86  .dma_stream = 6,
87  .dma_chan = 4
88 #endif
89  },
90  {
91  .dev = USART1,
92  .rcc_mask = RCC_APB2ENR_USART1EN,
93  .rx_pin = GPIO_PIN(PORT_A, 10),
94  .tx_pin = GPIO_PIN(PORT_A, 9),
95  .rx_af = GPIO_AF7,
96  .tx_af = GPIO_AF7,
97  .bus = APB2,
98  .irqn = USART1_IRQn,
99 #ifdef UART_USE_DMA
100  .dma_stream = 6,
101  .dma_chan = 3
102 #endif
103  },
104  {
105  .dev = USART6,
106  .rcc_mask = RCC_APB2ENR_USART6EN,
107  .rx_pin = GPIO_PIN(PORT_A, 12),
108  .tx_pin = GPIO_PIN(PORT_A, 11),
109  .rx_af = GPIO_AF8,
110  .tx_af = GPIO_AF8,
111  .bus = APB2,
112  .irqn = USART6_IRQn,
113 #ifdef UART_USE_DMA
114  .dma_stream = 6,
115  .dma_chan = 2
116 #endif
117  }
118 };
119 
120 /* assign ISR vector names */
121 #define UART_0_ISR isr_usart2
122 #define UART_0_DMA_ISR isr_dma1_stream6
123 #define UART_1_ISR isr_usart1
124 #define UART_1_DMA_ISR isr_dma1_stream6
125 #define UART_2_ISR isr_usart6
126 #define UART_2_DMA_ISR isr_dma1_stream6
127 
128 /* deduct number of defined UART interfaces */
129 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
130 
135 static const pwm_conf_t pwm_config[] = {
136  {
137  .dev = TIM2,
138  .rcc_mask = RCC_APB1ENR_TIM2EN,
139  .chan = { { .pin = GPIO_PIN(PORT_A, 15) , .cc_chan = 0 },
140  { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
141  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
142  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
143  .af = GPIO_AF1,
144  .bus = APB1
145  },
146  {
147  .dev = TIM3,
148  .rcc_mask = RCC_APB1ENR_TIM3EN,
149  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
150  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
151  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
152  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
153  .af = GPIO_AF2,
154  .bus = APB1
155  },
156 };
157 
158 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
159 
168 static const uint8_t spi_divtable[2][5] = {
169  { /* for APB1 @ 50000000Hz */
170  7, /* -> 195312Hz */
171  6, /* -> 390625Hz */
172  5, /* -> 781250Hz */
173  2, /* -> 6250000Hz */
174  1 /* -> 12500000Hz */
175  },
176  { /* for APB2 @ 100000000Hz */
177  7, /* -> 390625Hz */
178  7, /* -> 390625Hz */
179  6, /* -> 781250Hz */
180  3, /* -> 6250000Hz */
181  2 /* -> 12500000Hz */
182  }
183 };
184 
185 static const spi_conf_t spi_config[] = {
186  {
187  .dev = SPI1,
188  .mosi_pin = GPIO_PIN(PORT_A, 7),
189  .miso_pin = GPIO_PIN(PORT_A, 6),
190  .sclk_pin = GPIO_PIN(PORT_A, 5),
191  .cs_pin = GPIO_PIN(PORT_A, 4),
192  .af = GPIO_AF5,
193  .rccmask = RCC_APB2ENR_SPI1EN,
194  .apbbus = APB2
195  }
196 };
197 
198 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
199 
205 #define I2C_NUMOF (1U)
206 #define I2C_0_EN 1
207 #define I2C_IRQ_PRIO 1
208 #define I2C_APBCLK (CLOCK_APB1)
209 
210 /* I2C 0 device configuration */
211 #define I2C_0_DEV I2C1
212 #define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
213 #define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
214 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
215 #define I2C_0_EVT_ISR isr_i2c1_ev
216 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
217 #define I2C_0_ERR_ISR isr_i2c1_er
218 /* I2C 0 pin configuration */
219 #define I2C_0_SCL_PORT GPIOB
220 #define I2C_0_SCL_PIN 8
221 #define I2C_0_SCL_AF 4
222 #define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
223 #define I2C_0_SDA_PORT GPIOB
224 #define I2C_0_SDA_PIN 9
225 #define I2C_0_SDA_AF 4
226 #define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
227 
233 #define ADC_NUMOF (0)
234 
240 #define DAC_NUMOF (0)
241 
243 #ifdef __cplusplus
244 }
245 #endif
246 
247 #endif /* PERIPH_CONF_H_ */
248 
use alternate function 7
USART_TypeDef * dev
USART device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.