boards/nucleo-f411/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* 0: no external high speed crystal available
33  * else: actual crystal frequency [in Hz] */
34 #define CLOCK_HSE (8000000U)
35 /* 0: no external low speed crystal available,
36  * 1: external crystal available (always 32.768kHz) */
37 #define CLOCK_LSE (1)
38 /* give the target core clock (HCLK) frequency [in Hz],
39  * maximum: 100MHz */
40 #define CLOCK_CORECLOCK (96000000U)
41 /* peripheral clock setup */
42 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
43 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
44 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
45 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
46 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
47 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
48 
54 static const timer_conf_t timer_config[] = {
55  {
56  .dev = TIM5,
57  .max = 0xffffffff,
58  .rcc_mask = RCC_APB1ENR_TIM5EN,
59  .bus = APB1,
60  .irqn = TIM5_IRQn
61  }
62 };
63 
64 #define TIMER_0_ISR isr_tim5
65 #define TIMER_1_ISR isr_tim4
66 
67 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
68 
74 static const uart_conf_t uart_config[] = {
75  {
76  .dev = USART2,
77  .rcc_mask = RCC_APB1ENR_USART2EN,
78  .rx_pin = GPIO_PIN(PORT_A,3),
79  .tx_pin = GPIO_PIN(PORT_A,2),
80  .rx_af = GPIO_AF7,
81  .tx_af = GPIO_AF7,
82  .bus = APB1,
83  .irqn = USART2_IRQn,
84 #ifdef UART_USE_DMA
85  .dma_stream = 6,
86  .dma_chan = 4
87 #endif
88  },
89  {
90  .dev = USART1,
91  .rcc_mask = RCC_APB2ENR_USART1EN,
92  .rx_pin = GPIO_PIN(PORT_A, 10),
93  .tx_pin = GPIO_PIN(PORT_A, 9),
94  .rx_af = GPIO_AF7,
95  .tx_af = GPIO_AF7,
96  .bus = APB2,
97  .irqn = USART1_IRQn,
98 #ifdef UART_USE_DMA
99  .dma_stream = 6,
100  .dma_chan = 3
101 #endif
102  },
103  {
104  .dev = USART6,
105  .rcc_mask = RCC_APB2ENR_USART6EN,
106  .rx_pin = GPIO_PIN(PORT_A, 12),
107  .tx_pin = GPIO_PIN(PORT_A, 11),
108  .rx_af = GPIO_AF8,
109  .tx_af = GPIO_AF8,
110  .bus = APB2,
111  .irqn = USART6_IRQn,
112 #ifdef UART_USE_DMA
113  .dma_stream = 6,
114  .dma_chan = 2
115 #endif
116  }
117 };
118 
119 /* assign ISR vector names */
120 #define UART_0_ISR isr_usart2
121 #define UART_0_DMA_ISR isr_dma1_stream6
122 #define UART_1_ISR isr_usart1
123 #define UART_1_DMA_ISR isr_dma1_stream6
124 #define UART_2_ISR isr_usart6
125 #define UART_2_DMA_ISR isr_dma1_stream6
126 
127 /* deduct number of defined UART interfaces */
128 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
129 
134 static const pwm_conf_t pwm_config[] = {
135  {
136  .dev = TIM2,
137  .rcc_mask = RCC_APB1ENR_TIM2EN,
138  .chan = { { .pin = GPIO_PIN(PORT_A, 15) , .cc_chan = 0 },
139  { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
140  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
141  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
142  .af = GPIO_AF1,
143  .bus = APB1
144  },
145  {
146  .dev = TIM3,
147  .rcc_mask = RCC_APB1ENR_TIM3EN,
148  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
149  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
150  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
151  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
152  .af = GPIO_AF2,
153  .bus = APB1
154  },
155 };
156 
157 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
158 
167 static const uint8_t spi_divtable[2][5] = {
168  { /* for APB1 @ 50000000Hz */
169  7, /* -> 195312Hz */
170  6, /* -> 390625Hz */
171  5, /* -> 781250Hz */
172  2, /* -> 6250000Hz */
173  1 /* -> 12500000Hz */
174  },
175  { /* for APB2 @ 100000000Hz */
176  7, /* -> 390625Hz */
177  7, /* -> 390625Hz */
178  6, /* -> 781250Hz */
179  3, /* -> 6250000Hz */
180  2 /* -> 12500000Hz */
181  }
182 };
183 
184 static const spi_conf_t spi_config[] = {
185  {
186  .dev = SPI1,
187  .mosi_pin = GPIO_PIN(PORT_A, 7),
188  .miso_pin = GPIO_PIN(PORT_A, 6),
189  .sclk_pin = GPIO_PIN(PORT_A, 5),
190  .cs_pin = GPIO_PIN(PORT_A, 4),
191  .af = GPIO_AF5,
192  .rccmask = RCC_APB2ENR_SPI1EN,
193  .apbbus = APB2
194  }
195 };
196 
197 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
198 
204 #define I2C_NUMOF (1U)
205 #define I2C_0_EN 1
206 #define I2C_IRQ_PRIO 1
207 #define I2C_APBCLK (CLOCK_APB1)
208 
209 /* I2C 0 device configuration */
210 #define I2C_0_DEV I2C1
211 #define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
212 #define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
213 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
214 #define I2C_0_EVT_ISR isr_i2c1_ev
215 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
216 #define I2C_0_ERR_ISR isr_i2c1_er
217 /* I2C 0 pin configuration */
218 #define I2C_0_SCL_PORT GPIOB
219 #define I2C_0_SCL_PIN 8
220 #define I2C_0_SCL_AF 4
221 #define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
222 #define I2C_0_SDA_PORT GPIOB
223 #define I2C_0_SDA_PIN 9
224 #define I2C_0_SDA_AF 4
225 #define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
226 
238 #define ADC_NUMOF (6U)
239 #define ADC_CONFIG { \
240  {GPIO_PIN(PORT_A, 0), 0, 0}, \
241  {GPIO_PIN(PORT_A, 1), 0, 1}, \
242  {GPIO_PIN(PORT_A, 4), 0, 4}, \
243  {GPIO_PIN(PORT_B, 0), 0, 8}, \
244  {GPIO_PIN(PORT_C, 1), 0, 11}, \
245  {GPIO_PIN(PORT_C, 0), 0, 10}, \
246 }
247 
249 #ifdef __cplusplus
250 }
251 #endif
252 
253 #endif /* PERIPH_CONF_H */
254 
use alternate function 7
USART_TypeDef * dev
USART device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI module configuration options.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.