boards/nucleo-f411/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 100MHz */
39 #define CLOCK_CORECLOCK (96000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (8000000U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (1)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
53 
54 /* Main PLL factors */
55 #define CLOCK_PLL_M (4)
56 #define CLOCK_PLL_N (192)
57 #define CLOCK_PLL_P (4)
58 #define CLOCK_PLL_Q (8)
59 
65 static const timer_conf_t timer_config[] = {
66  {
67  .dev = TIM5,
68  .max = 0xffffffff,
69  .rcc_mask = RCC_APB1ENR_TIM5EN,
70  .bus = APB1,
71  .irqn = TIM5_IRQn
72  }
73 };
74 
75 #define TIMER_0_ISR isr_tim5
76 #define TIMER_1_ISR isr_tim4
77 
78 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
79 
85 static const uart_conf_t uart_config[] = {
86  {
87  .dev = USART2,
88  .rcc_mask = RCC_APB1ENR_USART2EN,
89  .rx_pin = GPIO_PIN(PORT_A,3),
90  .tx_pin = GPIO_PIN(PORT_A,2),
91  .rx_af = GPIO_AF7,
92  .tx_af = GPIO_AF7,
93  .bus = APB1,
94  .irqn = USART2_IRQn,
95 #ifdef UART_USE_DMA
96  .dma_stream = 6,
97  .dma_chan = 4
98 #endif
99  },
100  {
101  .dev = USART1,
102  .rcc_mask = RCC_APB2ENR_USART1EN,
103  .rx_pin = GPIO_PIN(PORT_A, 10),
104  .tx_pin = GPIO_PIN(PORT_A, 9),
105  .rx_af = GPIO_AF7,
106  .tx_af = GPIO_AF7,
107  .bus = APB2,
108  .irqn = USART1_IRQn,
109 #ifdef UART_USE_DMA
110  .dma_stream = 6,
111  .dma_chan = 3
112 #endif
113  },
114  {
115  .dev = USART6,
116  .rcc_mask = RCC_APB2ENR_USART6EN,
117  .rx_pin = GPIO_PIN(PORT_A, 12),
118  .tx_pin = GPIO_PIN(PORT_A, 11),
119  .rx_af = GPIO_AF8,
120  .tx_af = GPIO_AF8,
121  .bus = APB2,
122  .irqn = USART6_IRQn,
123 #ifdef UART_USE_DMA
124  .dma_stream = 6,
125  .dma_chan = 2
126 #endif
127  }
128 };
129 
130 /* assign ISR vector names */
131 #define UART_0_ISR isr_usart2
132 #define UART_0_DMA_ISR isr_dma1_stream6
133 #define UART_1_ISR isr_usart1
134 #define UART_1_DMA_ISR isr_dma1_stream6
135 #define UART_2_ISR isr_usart6
136 #define UART_2_DMA_ISR isr_dma1_stream6
137 
138 /* deduct number of defined UART interfaces */
139 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
140 
145 static const pwm_conf_t pwm_config[] = {
146  {
147  .dev = TIM2,
148  .rcc_mask = RCC_APB1ENR_TIM2EN,
149  .chan = { { .pin = GPIO_PIN(PORT_A, 15) , .cc_chan = 0 },
150  { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
151  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
152  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
153  .af = GPIO_AF1,
154  .bus = APB1
155  },
156  {
157  .dev = TIM3,
158  .rcc_mask = RCC_APB1ENR_TIM3EN,
159  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
160  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
161  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
162  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
163  .af = GPIO_AF2,
164  .bus = APB1
165  },
166 };
167 
168 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
169 
178 static const uint8_t spi_divtable[2][5] = {
179  { /* for APB1 @ 48000000Hz */
180  7, /* -> 187500Hz */
181  6, /* -> 375000Hz */
182  5, /* -> 750000Hz */
183  2, /* -> 6000000Hz */
184  1 /* -> 12000000Hz */
185  },
186  { /* for APB2 @ 96000000Hz */
187  7, /* -> 375000Hz */
188  7, /* -> 375000Hz */
189  6, /* -> 750000Hz */
190  3, /* -> 6000000Hz */
191  2 /* -> 12000000Hz */
192  }
193 };
194 
195 static const spi_conf_t spi_config[] = {
196  {
197  .dev = SPI1,
198  .mosi_pin = GPIO_PIN(PORT_A, 7),
199  .miso_pin = GPIO_PIN(PORT_A, 6),
200  .sclk_pin = GPIO_PIN(PORT_A, 5),
201  .cs_pin = GPIO_PIN(PORT_A, 4),
202  .af = GPIO_AF5,
203  .rccmask = RCC_APB2ENR_SPI1EN,
204  .apbbus = APB2
205  }
206 };
207 
208 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
209 
215 #define I2C_NUMOF (1U)
216 #define I2C_0_EN 1
217 #define I2C_IRQ_PRIO 1
218 #define I2C_APBCLK (CLOCK_APB1)
219 
220 /* I2C 0 device configuration */
221 #define I2C_0_DEV I2C1
222 #define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
223 #define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
224 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
225 #define I2C_0_EVT_ISR isr_i2c1_ev
226 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
227 #define I2C_0_ERR_ISR isr_i2c1_er
228 /* I2C 0 pin configuration */
229 #define I2C_0_SCL_PORT GPIOB
230 #define I2C_0_SCL_PIN 8
231 #define I2C_0_SCL_AF 4
232 #define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
233 #define I2C_0_SDA_PORT GPIOB
234 #define I2C_0_SDA_PIN 9
235 #define I2C_0_SDA_AF 4
236 #define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
237 
249 #define ADC_NUMOF (6U)
250 #define ADC_CONFIG { \
251  {GPIO_PIN(PORT_A, 0), 0, 0}, \
252  {GPIO_PIN(PORT_A, 1), 0, 1}, \
253  {GPIO_PIN(PORT_A, 4), 0, 4}, \
254  {GPIO_PIN(PORT_B, 0), 0, 8}, \
255  {GPIO_PIN(PORT_C, 1), 0, 11}, \
256  {GPIO_PIN(PORT_C, 0), 0, 10}, \
257 }
258 
260 #ifdef __cplusplus
261 }
262 #endif
263 
264 #endif /* PERIPH_CONF_H */
265 
use alternate function 7
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
use alternate function 8
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.