boards/nucleo-f410/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* 0: no external high speed crystal available
33  * else: actual crystal frequency [in Hz] */
34 #define CLOCK_HSE (8000000U)
35 /* 0: no external low speed crystal available,
36  * 1: external crystal available (always 32.768kHz) */
37 #define CLOCK_LSE (1)
38 /* give the target core clock (HCLK) frequency [in Hz],
39  * maximum: 100MHz */
40 #define CLOCK_CORECLOCK (96000000U)
41 /* peripheral clock setup */
42 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
43 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
44 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
45 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
46 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
47 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
48 
54 static const timer_conf_t timer_config[] = {
55  {
56  .dev = TIM5,
57  .max = 0xffffffff,
58  .rcc_mask = RCC_APB1ENR_TIM5EN,
59  .bus = APB1,
60  .irqn = TIM5_IRQn
61  }
62 };
63 
64 #define TIMER_0_ISR isr_tim5
65 
66 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
67 
73 static const uart_conf_t uart_config[] = {
74  {
75  .dev = USART2,
76  .rcc_mask = RCC_APB1ENR_USART2EN,
77  .rx_pin = GPIO_PIN(PORT_A, 3),
78  .tx_pin = GPIO_PIN(PORT_A, 2),
79  .rx_af = GPIO_AF7,
80  .tx_af = GPIO_AF7,
81  .bus = APB1,
82  .irqn = USART2_IRQn,
83 #ifdef UART_USE_DMA
84  .dma_stream = 6,
85  .dma_chan = 4
86 #endif
87  },
88  {
89  .dev = USART1,
90  .rcc_mask = RCC_APB2ENR_USART1EN,
91  .rx_pin = GPIO_PIN(PORT_A, 10),
92  .tx_pin = GPIO_PIN(PORT_A, 9),
93  .rx_af = GPIO_AF7,
94  .tx_af = GPIO_AF7,
95  .bus = APB2,
96  .irqn = USART1_IRQn,
97 #ifdef UART_USE_DMA
98  .dma_stream = 5,
99  .dma_chan = 4
100 #endif
101  }
102 };
103 
104 /* assign ISR vector names */
105 #define UART_0_ISR (isr_usart2)
106 #define UART_0_DMA_ISR (isr_dma1_stream6)
107 #define UART_1_ISR (isr_usart1)
108 #define UART_1_DMA_ISR (isr_dma1_stream5)
109 
110 /* deduct number of defined UART interfaces */
111 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
112 
121 static const uint8_t spi_divtable[2][5] = {
122  { /* for APB1 @ 50000000Hz */
123  7, /* -> 195312Hz */
124  6, /* -> 390625Hz */
125  5, /* -> 781250Hz */
126  2, /* -> 6250000Hz */
127  1 /* -> 12500000Hz */
128  },
129  { /* for APB2 @ 100000000Hz */
130  7, /* -> 390625Hz */
131  7, /* -> 390625Hz */
132  6, /* -> 781250Hz */
133  3, /* -> 6250000Hz */
134  2 /* -> 12500000Hz */
135  }
136 };
137 
138 static const spi_conf_t spi_config[] = {
139  {
140  .dev = SPI1,
141  .mosi_pin = GPIO_PIN(PORT_A, 7),
142  .miso_pin = GPIO_PIN(PORT_A, 6),
143  .sclk_pin = GPIO_PIN(PORT_A, 5),
144  .cs_pin = GPIO_PIN(PORT_A, 4),
145  .af = GPIO_AF5,
146  .rccmask = RCC_APB2ENR_SPI1EN,
147  .apbbus = APB2
148  }
149 };
150 
151 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
152 
158 #define I2C_NUMOF (1U)
159 #define I2C_0_EN 1
160 #define I2C_IRQ_PRIO 1
161 #define I2C_APBCLK (CLOCK_APB1)
162 
163 /* I2C 0 device configuration */
164 #define I2C_0_DEV I2C1
165 #define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
166 #define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
167 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
168 #define I2C_0_EVT_ISR isr_i2c1_ev
169 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
170 #define I2C_0_ERR_ISR isr_i2c1_er
171 /* I2C 0 pin configuration */
172 #define I2C_0_SCL_PORT GPIOB
173 #define I2C_0_SCL_PIN 8
174 #define I2C_0_SCL_AF 4
175 #define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
176 #define I2C_0_SDA_PORT GPIOB
177 #define I2C_0_SDA_PIN 9
178 #define I2C_0_SDA_AF 4
179 #define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
180 
192 #define ADC_NUMOF (6U)
193 #define ADC_CONFIG { \
194  {GPIO_PIN(PORT_A, 0), 0, 0}, \
195  {GPIO_PIN(PORT_A, 1), 0, 1}, \
196  {GPIO_PIN(PORT_A, 4), 0, 4}, \
197  {GPIO_PIN(PORT_B, 0), 0, 8}, \
198  {GPIO_PIN(PORT_C, 1), 0, 11}, \
199  {GPIO_PIN(PORT_C, 0), 0, 10}, \
200 }
201 
203 #ifdef __cplusplus
204 }
205 #endif
206 
207 #endif /* PERIPH_CONF_H */
208 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 5
UART device configuration.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.