boards/nucleo-f410/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLOCK_HSE (8000000U) /* external oscillator */
33 #define CLOCK_CORECLOCK (100000000U) /* desired core clock frequency */
34 
35 /* the actual PLL values are automatically generated */
36 #define CLOCK_PLL_M (CLOCK_HSE / 1000000)
37 #define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
38 #define CLOCK_PLL_P (2U)
39 #define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
40 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
41 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
42 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
43 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
44 
45 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
48 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
49 
55 static const timer_conf_t timer_config[] = {
56  {
57  .dev = TIM5,
58  .max = 0xffffffff,
59  .rcc_mask = RCC_APB1ENR_TIM5EN,
60  .bus = APB1,
61  .irqn = TIM5_IRQn
62  }
63 };
64 
65 #define TIMER_0_ISR isr_tim5
66 
67 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
68 
74 static const uart_conf_t uart_config[] = {
75  {
76  .dev = USART2,
77  .rcc_mask = RCC_APB1ENR_USART2EN,
78  .rx_pin = GPIO_PIN(PORT_A, 3),
79  .tx_pin = GPIO_PIN(PORT_A, 2),
80  .rx_af = GPIO_AF7,
81  .tx_af = GPIO_AF7,
82  .bus = APB1,
83  .irqn = USART2_IRQn,
84 #ifdef UART_USE_DMA
85  .dma_stream = 6,
86  .dma_chan = 4
87 #endif
88  },
89  {
90  .dev = USART1,
91  .rcc_mask = RCC_APB2ENR_USART1EN,
92  .rx_pin = GPIO_PIN(PORT_A, 10),
93  .tx_pin = GPIO_PIN(PORT_A, 9),
94  .rx_af = GPIO_AF7,
95  .tx_af = GPIO_AF7,
96  .bus = APB2,
97  .irqn = USART1_IRQn,
98 #ifdef UART_USE_DMA
99  .dma_stream = 5,
100  .dma_chan = 4
101 #endif
102  }
103 };
104 
105 /* assign ISR vector names */
106 #define UART_0_ISR (isr_usart2)
107 #define UART_0_DMA_ISR (isr_dma1_stream6)
108 #define UART_1_ISR (isr_usart1)
109 #define UART_1_DMA_ISR (isr_dma1_stream5)
110 
111 /* deduct number of defined UART interfaces */
112 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
113 
122 static const uint8_t spi_divtable[2][5] = {
123  { /* for APB1 @ 50000000Hz */
124  7, /* -> 195312Hz */
125  6, /* -> 390625Hz */
126  5, /* -> 781250Hz */
127  2, /* -> 6250000Hz */
128  1 /* -> 12500000Hz */
129  },
130  { /* for APB2 @ 100000000Hz */
131  7, /* -> 390625Hz */
132  7, /* -> 390625Hz */
133  6, /* -> 781250Hz */
134  3, /* -> 6250000Hz */
135  2 /* -> 12500000Hz */
136  }
137 };
138 
139 static const spi_conf_t spi_config[] = {
140  {
141  .dev = SPI1,
142  .mosi_pin = GPIO_PIN(PORT_A, 7),
143  .miso_pin = GPIO_PIN(PORT_A, 6),
144  .sclk_pin = GPIO_PIN(PORT_A, 5),
145  .cs_pin = GPIO_PIN(PORT_A, 4),
146  .af = GPIO_AF5,
147  .rccmask = RCC_APB2ENR_SPI1EN,
148  .apbbus = APB2
149  }
150 };
151 
152 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
153 
159 #define I2C_NUMOF (1U)
160 #define I2C_0_EN 1
161 #define I2C_IRQ_PRIO 1
162 #define I2C_APBCLK (CLOCK_APB1)
163 
164 /* I2C 0 device configuration */
165 #define I2C_0_DEV I2C1
166 #define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
167 #define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
168 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
169 #define I2C_0_EVT_ISR isr_i2c1_ev
170 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
171 #define I2C_0_ERR_ISR isr_i2c1_er
172 /* I2C 0 pin configuration */
173 #define I2C_0_SCL_PORT GPIOB
174 #define I2C_0_SCL_PIN 8
175 #define I2C_0_SCL_AF 4
176 #define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
177 #define I2C_0_SDA_PORT GPIOB
178 #define I2C_0_SDA_PIN 9
179 #define I2C_0_SDA_AF 4
180 #define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
181 
187 #define ADC_NUMOF (0)
188 
194 #define DAC_NUMOF (0)
195 
197 #ifdef __cplusplus
198 }
199 #endif
200 
201 #endif /* PERIPH_CONF_H */
202 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 5
UART device configuration.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
cc2538_ssi_t * dev
SSI device.