boards/nucleo-f410/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 100MHz */
39 #define CLOCK_CORECLOCK (96000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (8000000U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (1)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
53 
54 /* Main PLL factors */
55 #define CLOCK_PLL_M (4)
56 #define CLOCK_PLL_N (192)
57 #define CLOCK_PLL_P (4)
58 #define CLOCK_PLL_Q (8)
59 
65 static const timer_conf_t timer_config[] = {
66  {
67  .dev = TIM5,
68  .max = 0xffffffff,
69  .rcc_mask = RCC_APB1ENR_TIM5EN,
70  .bus = APB1,
71  .irqn = TIM5_IRQn
72  }
73 };
74 
75 #define TIMER_0_ISR isr_tim5
76 
77 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
78 
84 static const uart_conf_t uart_config[] = {
85  {
86  .dev = USART2,
87  .rcc_mask = RCC_APB1ENR_USART2EN,
88  .rx_pin = GPIO_PIN(PORT_A, 3),
89  .tx_pin = GPIO_PIN(PORT_A, 2),
90  .rx_af = GPIO_AF7,
91  .tx_af = GPIO_AF7,
92  .bus = APB1,
93  .irqn = USART2_IRQn,
94 #ifdef UART_USE_DMA
95  .dma_stream = 6,
96  .dma_chan = 4
97 #endif
98  },
99  {
100  .dev = USART1,
101  .rcc_mask = RCC_APB2ENR_USART1EN,
102  .rx_pin = GPIO_PIN(PORT_A, 10),
103  .tx_pin = GPIO_PIN(PORT_A, 9),
104  .rx_af = GPIO_AF7,
105  .tx_af = GPIO_AF7,
106  .bus = APB2,
107  .irqn = USART1_IRQn,
108 #ifdef UART_USE_DMA
109  .dma_stream = 5,
110  .dma_chan = 4
111 #endif
112  }
113 };
114 
115 /* assign ISR vector names */
116 #define UART_0_ISR (isr_usart2)
117 #define UART_0_DMA_ISR (isr_dma1_stream6)
118 #define UART_1_ISR (isr_usart1)
119 #define UART_1_DMA_ISR (isr_dma1_stream5)
120 
121 /* deduct number of defined UART interfaces */
122 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
123 
132 static const uint8_t spi_divtable[2][5] = {
133  { /* for APB1 @ 48000000Hz */
134  7, /* -> 187500Hz */
135  6, /* -> 375000Hz */
136  5, /* -> 750000Hz */
137  2, /* -> 6000000Hz */
138  1 /* -> 12000000Hz */
139  },
140  { /* for APB2 @ 96000000Hz */
141  7, /* -> 375000Hz */
142  7, /* -> 375000Hz */
143  6, /* -> 750000Hz */
144  3, /* -> 6000000Hz */
145  2 /* -> 12000000Hz */
146  }
147 };
148 
149 static const spi_conf_t spi_config[] = {
150  {
151  .dev = SPI1,
152  .mosi_pin = GPIO_PIN(PORT_A, 7),
153  .miso_pin = GPIO_PIN(PORT_A, 6),
154  .sclk_pin = GPIO_PIN(PORT_A, 5),
155  .cs_pin = GPIO_PIN(PORT_A, 4),
156  .af = GPIO_AF5,
157  .rccmask = RCC_APB2ENR_SPI1EN,
158  .apbbus = APB2
159  }
160 };
161 
162 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
163 
169 #define I2C_NUMOF (1U)
170 #define I2C_0_EN 1
171 #define I2C_IRQ_PRIO 1
172 #define I2C_APBCLK (CLOCK_APB1)
173 
174 /* I2C 0 device configuration */
175 #define I2C_0_DEV I2C1
176 #define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
177 #define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
178 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
179 #define I2C_0_EVT_ISR isr_i2c1_ev
180 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
181 #define I2C_0_ERR_ISR isr_i2c1_er
182 /* I2C 0 pin configuration */
183 #define I2C_0_SCL_PORT GPIOB
184 #define I2C_0_SCL_PIN 8
185 #define I2C_0_SCL_AF 4
186 #define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
187 #define I2C_0_SDA_PORT GPIOB
188 #define I2C_0_SDA_PIN 9
189 #define I2C_0_SDA_AF 4
190 #define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
191 
203 #define ADC_NUMOF (6U)
204 #define ADC_CONFIG { \
205  {GPIO_PIN(PORT_A, 0), 0, 0}, \
206  {GPIO_PIN(PORT_A, 1), 0, 1}, \
207  {GPIO_PIN(PORT_A, 4), 0, 4}, \
208  {GPIO_PIN(PORT_B, 0), 0, 8}, \
209  {GPIO_PIN(PORT_C, 1), 0, 11}, \
210  {GPIO_PIN(PORT_C, 0), 0, 10}, \
211 }
212 
214 #ifdef __cplusplus
215 }
216 #endif
217 
218 #endif /* PERIPH_CONF_H */
219 
use alternate function 7
cc2538_uart_t * dev
pointer to the used UART device
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
cc2538_ssi_t * dev
SSI device.