boards/nucleo-f410/include/periph_conf.h
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1 /*
2  * Copyright (C) 2016 Inria
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 100MHz */
37 #define CLOCK_CORECLOCK (96000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (8000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (1)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 50MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
49 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 100MHz */
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
51 
52 /* Main PLL factors */
53 #define CLOCK_PLL_M (4)
54 #define CLOCK_PLL_N (192)
55 #define CLOCK_PLL_P (4)
56 #define CLOCK_PLL_Q (8)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM5,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM5EN,
68  .bus = APB1,
69  .irqn = TIM5_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim5
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART2,
85  .rcc_mask = RCC_APB1ENR_USART2EN,
86  .rx_pin = GPIO_PIN(PORT_A, 3),
87  .tx_pin = GPIO_PIN(PORT_A, 2),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB1,
91  .irqn = USART2_IRQn,
92 #ifdef UART_USE_DMA
93  .dma_stream = 6,
94  .dma_chan = 4
95 #endif
96  },
97  {
98  .dev = USART1,
99  .rcc_mask = RCC_APB2ENR_USART1EN,
100  .rx_pin = GPIO_PIN(PORT_A, 10),
101  .tx_pin = GPIO_PIN(PORT_A, 9),
102  .rx_af = GPIO_AF7,
103  .tx_af = GPIO_AF7,
104  .bus = APB2,
105  .irqn = USART1_IRQn,
106 #ifdef UART_USE_DMA
107  .dma_stream = 5,
108  .dma_chan = 4
109 #endif
110  }
111 };
112 
113 /* assign ISR vector names */
114 #define UART_0_ISR (isr_usart2)
115 #define UART_0_DMA_ISR (isr_dma1_stream6)
116 #define UART_1_ISR (isr_usart1)
117 #define UART_1_DMA_ISR (isr_dma1_stream5)
118 
119 /* deduct number of defined UART interfaces */
120 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
121 
130 static const uint8_t spi_divtable[2][5] = {
131  { /* for APB1 @ 48000000Hz */
132  7, /* -> 187500Hz */
133  6, /* -> 375000Hz */
134  5, /* -> 750000Hz */
135  2, /* -> 6000000Hz */
136  1 /* -> 12000000Hz */
137  },
138  { /* for APB2 @ 96000000Hz */
139  7, /* -> 375000Hz */
140  7, /* -> 375000Hz */
141  6, /* -> 750000Hz */
142  3, /* -> 6000000Hz */
143  2 /* -> 12000000Hz */
144  }
145 };
146 
147 static const spi_conf_t spi_config[] = {
148  {
149  .dev = SPI1,
150  .mosi_pin = GPIO_PIN(PORT_A, 7),
151  .miso_pin = GPIO_PIN(PORT_A, 6),
152  .sclk_pin = GPIO_PIN(PORT_A, 5),
153  .cs_pin = GPIO_PIN(PORT_A, 4),
154  .af = GPIO_AF5,
155  .rccmask = RCC_APB2ENR_SPI1EN,
156  .apbbus = APB2
157  }
158 };
159 
160 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
161 
167 #define I2C_NUMOF (1U)
168 #define I2C_0_EN 1
169 #define I2C_IRQ_PRIO 1
170 #define I2C_APBCLK (CLOCK_APB1)
171 
172 /* I2C 0 device configuration */
173 #define I2C_0_DEV I2C1
174 #define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
175 #define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
176 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
177 #define I2C_0_EVT_ISR isr_i2c1_ev
178 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
179 #define I2C_0_ERR_ISR isr_i2c1_er
180 /* I2C 0 pin configuration */
181 #define I2C_0_SCL_PORT GPIOB
182 #define I2C_0_SCL_PIN 8
183 #define I2C_0_SCL_AF 4
184 #define I2C_0_SCL_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
185 #define I2C_0_SDA_PORT GPIOB
186 #define I2C_0_SDA_PIN 9
187 #define I2C_0_SDA_AF 4
188 #define I2C_0_SDA_CLKEN() (RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN)
189 
201 #define ADC_NUMOF (6U)
202 #define ADC_CONFIG { \
203  {GPIO_PIN(PORT_A, 0), 0, 0}, \
204  {GPIO_PIN(PORT_A, 1), 0, 1}, \
205  {GPIO_PIN(PORT_A, 4), 0, 4}, \
206  {GPIO_PIN(PORT_B, 0), 0, 8}, \
207  {GPIO_PIN(PORT_C, 1), 0, 11}, \
208  {GPIO_PIN(PORT_C, 0), 0, 10}, \
209 }
210 
212 #ifdef __cplusplus
213 }
214 #endif
215 
216 #endif /* PERIPH_CONF_H */
217 
use alternate function 7
USART_TypeDef * dev
USART device used.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
SPI module configuration options.
Timer configuration.
cc2538_ssi_t * dev
SSI device.