boards/nucleo-f401/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Lari Lehtomäki
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
21 #ifndef PERIPH_CONF_H
22 #define PERIPH_CONF_H
23 
24 #include "periph_cpu.h"
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
37 /* give the target core clock (HCLK) frequency [in Hz],
38  * maximum: 84MHz */
39 #define CLOCK_CORECLOCK (84000000U)
40 /* 0: no external high speed crystal available
41  * else: actual crystal frequency [in Hz] */
42 #define CLOCK_HSE (8000000U)
43 /* 0: no external low speed crystal available,
44  * 1: external crystal available (always 32.768kHz) */
45 #define CLOCK_LSE (1)
46 /* peripheral clock setup */
47 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
48 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
49 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */
50 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
51 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */
52 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
53 
54 /* Main PLL factors */
55 #define CLOCK_PLL_M (4)
56 #define CLOCK_PLL_N (168)
57 #define CLOCK_PLL_P (4)
58 #define CLOCK_PLL_Q (7)
59 
65 static const timer_conf_t timer_config[] = {
66  {
67  .dev = TIM5,
68  .max = 0xffffffff,
69  .rcc_mask = RCC_APB1ENR_TIM5EN,
70  .bus = APB1,
71  .irqn = TIM5_IRQn
72  }
73 };
74 
75 #define TIMER_0_ISR isr_tim5
76 
77 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
78 
84 static const uart_conf_t uart_config[] = {
85  {
86  .dev = USART2,
87  .rcc_mask = RCC_APB1ENR_USART2EN,
88  .rx_pin = GPIO_PIN(PORT_A, 3),
89  .tx_pin = GPIO_PIN(PORT_A, 2),
90  .rx_af = GPIO_AF7,
91  .tx_af = GPIO_AF7,
92  .bus = APB1,
93  .irqn = USART2_IRQn,
94 #ifdef UART_USE_DMA
95  .dma_stream = 6,
96  .dma_chan = 4
97 #endif
98  },
99  {
100  .dev = USART6,
101  .rcc_mask = RCC_APB2ENR_USART6EN,
102  .rx_pin = GPIO_PIN(PORT_A, 12),
103  .tx_pin = GPIO_PIN(PORT_A, 11),
104  .rx_af = GPIO_AF8,
105  .tx_af = GPIO_AF8,
106  .bus = APB2,
107  .irqn = USART6_IRQn,
108 #ifdef UART_USE_DMA
109  .dma_stream = 6,
110  .dma_chan = 4
111 #endif
112  }
113 };
114 
115 #define UART_0_ISR (isr_usart2)
116 #define UART_0_DMA_ISR (isr_dma1_stream6)
117 #define UART_1_ISR (isr_usart6)
118 #define UART_1_DMA_ISR (isr_dma1_stream6)
119 
120 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
121 
127 static const pwm_conf_t pwm_config[] = {
128  {
129  .dev = TIM2,
130  .rcc_mask = RCC_APB1ENR_TIM2EN,
131  .chan = { { .pin = GPIO_PIN(PORT_A, 15) , .cc_chan = 0 },
132  { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
133  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
134  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
135  .af = GPIO_AF1,
136  .bus = APB1
137  },
138 };
139 
140 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
141 
147 static const qdec_conf_t qdec_config[] = {
148  {
149  .dev = TIM3,
150  .max = 0xffffffff,
151  .rcc_mask = RCC_APB1ENR_TIM3EN,
152  .chan = { { .pin = GPIO_PIN(PORT_A, 6), .cc_chan = 0 },
153  { .pin = GPIO_PIN(PORT_A, 7), .cc_chan = 1 } },
154  .af = GPIO_AF2,
155  .bus = APB1,
156  .irqn = TIM3_IRQn
157  },
158  {
159  .dev = TIM4,
160  .max = 0xffffffff,
161  .rcc_mask = RCC_APB1ENR_TIM4EN,
162  .chan = { { .pin = GPIO_PIN(PORT_B, 6), .cc_chan = 0 },
163  { .pin = GPIO_PIN(PORT_B, 7), .cc_chan = 1 } },
164  .af = GPIO_AF2,
165  .bus = APB1,
166  .irqn = TIM4_IRQn
167  },
168 };
169 
170 #define QDEC_0_ISR isr_tim3
171 #define QDEC_1_ISR isr_tim4
172 
173 #define QDEC_NUMOF (sizeof(qdec_config) / sizeof(qdec_config[0]))
174 
183 static const uint8_t spi_divtable[2][5] = {
184  { /* for APB1 @ 42000000Hz */
185  7, /* -> 164062Hz */
186  6, /* -> 328125Hz */
187  4, /* -> 1312500Hz */
188  2, /* -> 5250000Hz */
189  1 /* -> 10500000Hz */
190  },
191  { /* for APB2 @ 84000000Hz */
192  7, /* -> 328125Hz */
193  7, /* -> 328125Hz */
194  5, /* -> 1312500Hz */
195  3, /* -> 5250000Hz */
196  2 /* -> 10500000Hz */
197  }
198 };
199 
200 static const spi_conf_t spi_config[] = {
201  {
202  .dev = SPI1,
203  .mosi_pin = GPIO_PIN(PORT_A, 7),
204  .miso_pin = GPIO_PIN(PORT_A, 6),
205  .sclk_pin = GPIO_PIN(PORT_A, 5),
206  .cs_pin = GPIO_PIN(PORT_A, 4),
207  .af = GPIO_AF5,
208  .rccmask = RCC_APB2ENR_SPI1EN,
209  .apbbus = APB2
210  },
211  {
212  .dev = SPI2,
213  .mosi_pin = GPIO_PIN(PORT_B, 15),
214  .miso_pin = GPIO_PIN(PORT_B, 14),
215  .sclk_pin = GPIO_PIN(PORT_B, 13),
216  .cs_pin = GPIO_PIN(PORT_B, 12),
217  .af = GPIO_AF5,
218  .rccmask = RCC_APB1ENR_SPI2EN,
219  .apbbus = APB1
220  },
221  {
222  .dev = SPI3,
223  .mosi_pin = GPIO_PIN(PORT_C, 12),
224  .miso_pin = GPIO_PIN(PORT_C, 11),
225  .sclk_pin = GPIO_PIN(PORT_C, 10),
226  .cs_pin = GPIO_UNDEF,
227  .af = GPIO_AF6,
228  .rccmask = RCC_APB1ENR_SPI3EN,
229  .apbbus = APB1
230  }
231 };
232 
233 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
234 
241 #define I2C_NUMOF (1U)
242 #define I2C_0_EN 1
243 #define I2C_IRQ_PRIO 1
244 #define I2C_APBCLK (CLOCK_APB1)
245 
246 /* I2C 0 device configuration */
247 #define I2C_0_DEV I2C1
248 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
249 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
250 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
251 #define I2C_0_EVT_ISR isr_i2c1_ev
252 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
253 #define I2C_0_ERR_ISR isr_i2c1_er
254 /* I2C 0 pin configuration */
255 #define I2C_0_SCL_PORT GPIOB
256 #define I2C_0_SCL_PIN 8
257 #define I2C_0_SCL_AF 4
258 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
259 #define I2C_0_SDA_PORT GPIOB
260 #define I2C_0_SDA_PIN 9
261 #define I2C_0_SDA_AF 4
262 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
263 
275 #define ADC_NUMOF (6U)
276 #define ADC_CONFIG { \
277  {GPIO_PIN(PORT_A, 0), 0, 0}, \
278  {GPIO_PIN(PORT_A, 1), 0, 1}, \
279  {GPIO_PIN(PORT_A, 4), 0, 4}, \
280  {GPIO_PIN(PORT_B, 0), 0, 8}, \
281  {GPIO_PIN(PORT_C, 1), 0, 11}, \
282  {GPIO_PIN(PORT_C, 0), 0, 10}, \
283 }
284 
290 #define RTC_NUMOF (1)
291 
293 #ifdef __cplusplus
294 }
295 #endif
296 
297 #endif /* PERIPH_CONF_H */
298 
use alternate function 7
cc2538_uart_t * dev
pointer to the used UART device
TIMER_TypeDef * dev
TIMER device used.
use alternate function 8
use alternate function 6
TIM_TypeDef * dev
Timer used.
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
SPI module configuration options.
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.