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boards/nucleo-f401/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Lari Lehtomäki
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 #define CLOCK_HSE (8000000U) /* external oscillator */
33 #define CLOCK_CORECLOCK (84000000U) /* desired core clock frequency */
34 
35 /* the actual PLL values are automatically generated */
36 #define CLOCK_PLL_M (CLOCK_HSE / 1000000)
37 #define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
38 #define CLOCK_PLL_P (2U)
39 #define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
40 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
41 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
42 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
43 #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
44 
45 /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
48 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
49 
55 static const timer_conf_t timer_config[] = {
56  {
57  .dev = TIM5,
58  .max = 0xffffffff,
59  .rcc_mask = RCC_APB1ENR_TIM5EN,
60  .bus = APB1,
61  .irqn = TIM5_IRQn
62  }
63 };
64 
65 #define TIMER_0_ISR isr_tim5
66 
67 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
68 
74 static const uart_conf_t uart_config[] = {
75  {
76  .dev = USART2,
77  .rcc_mask = RCC_APB1ENR_USART2EN,
78  .rx_pin = GPIO_PIN(PORT_A, 3),
79  .tx_pin = GPIO_PIN(PORT_A, 2),
80  .rx_af = GPIO_AF7,
81  .tx_af = GPIO_AF7,
82  .bus = APB1,
83  .irqn = USART2_IRQn,
84 #ifdef UART_USE_DMA
85  .dma_stream = 6,
86  .dma_chan = 4
87 #endif
88  },
89  {
90  .dev = USART6,
91  .rcc_mask = RCC_APB2ENR_USART6EN,
92  .rx_pin = GPIO_PIN(PORT_A, 12),
93  .tx_pin = GPIO_PIN(PORT_A, 11),
94  .rx_af = GPIO_AF8,
95  .tx_af = GPIO_AF8,
96  .bus = APB2,
97  .irqn = USART6_IRQn,
98 #ifdef UART_USE_DMA
99  .dma_stream = 6,
100  .dma_chan = 4
101 #endif
102  }
103 };
104 
105 #define UART_0_ISR (isr_usart2)
106 #define UART_0_DMA_ISR (isr_dma1_stream6)
107 #define UART_1_ISR (isr_usart6)
108 #define UART_1_DMA_ISR (isr_dma1_stream6)
109 
110 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
111 
117 static const pwm_conf_t pwm_config[] = {
118  {
119  .dev = TIM2,
120  .rcc_mask = RCC_APB1ENR_TIM2EN,
121  .chan = { { .pin = GPIO_PIN(PORT_A, 15) , .cc_chan = 0 },
122  { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
123  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
124  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
125  .af = GPIO_AF1,
126  .bus = APB1
127  },
128  {
129  .dev = TIM3,
130  .rcc_mask = RCC_APB1ENR_TIM3EN,
131  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
132  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
133  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
134  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
135  .af = GPIO_AF2,
136  .bus = APB1
137  },
138 };
139 
140 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
141 
150 static const uint8_t spi_divtable[2][5] = {
151  { /* for APB1 @ 42000000Hz */
152  7, /* -> 164062Hz */
153  6, /* -> 328125Hz */
154  4, /* -> 1312500Hz */
155  2, /* -> 5250000Hz */
156  1 /* -> 10500000Hz */
157  },
158  { /* for APB2 @ 84000000Hz */
159  7, /* -> 328125Hz */
160  7, /* -> 328125Hz */
161  5, /* -> 1312500Hz */
162  3, /* -> 5250000Hz */
163  2 /* -> 10500000Hz */
164  }
165 };
166 
167 static const spi_conf_t spi_config[] = {
168  {
169  .dev = SPI1,
170  .mosi_pin = GPIO_PIN(PORT_A, 7),
171  .miso_pin = GPIO_PIN(PORT_A, 6),
172  .sclk_pin = GPIO_PIN(PORT_A, 5),
173  .cs_pin = GPIO_PIN(PORT_A, 4),
174  .af = GPIO_AF5,
175  .rccmask = RCC_APB2ENR_SPI1EN,
176  .apbbus = APB2
177  },
178  {
179  .dev = SPI2,
180  .mosi_pin = GPIO_PIN(PORT_B, 15),
181  .miso_pin = GPIO_PIN(PORT_B, 14),
182  .sclk_pin = GPIO_PIN(PORT_B, 13),
183  .cs_pin = GPIO_PIN(PORT_B, 12),
184  .af = GPIO_AF5,
185  .rccmask = RCC_APB1ENR_SPI2EN,
186  .apbbus = APB1
187  },
188  {
189  .dev = SPI3,
190  .mosi_pin = GPIO_PIN(PORT_C, 12),
191  .miso_pin = GPIO_PIN(PORT_C, 11),
192  .sclk_pin = GPIO_PIN(PORT_C, 10),
193  .cs_pin = GPIO_UNDEF,
194  .af = GPIO_AF6,
195  .rccmask = RCC_APB1ENR_SPI3EN,
196  .apbbus = APB1
197  }
198 };
199 
200 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
201 
208 #define I2C_NUMOF (1U)
209 #define I2C_0_EN 1
210 #define I2C_IRQ_PRIO 1
211 #define I2C_APBCLK (42000000U)
212 
213 /* I2C 0 device configuration */
214 #define I2C_0_DEV I2C1
215 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
216 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
217 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
218 #define I2C_0_EVT_ISR isr_i2c1_ev
219 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
220 #define I2C_0_ERR_ISR isr_i2c1_er
221 /* I2C 0 pin configuration */
222 #define I2C_0_SCL_PORT GPIOB
223 #define I2C_0_SCL_PIN 8
224 #define I2C_0_SCL_AF 4
225 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
226 #define I2C_0_SDA_PORT GPIOB
227 #define I2C_0_SDA_PIN 9
228 #define I2C_0_SDA_AF 4
229 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
230 
236 #define ADC_NUMOF (0)
237 
243 #define DAC_NUMOF (0)
244 
250 #define RTC_NUMOF (1)
251 
253 #ifdef __cplusplus
254 }
255 #endif
256 
257 #endif /* PERIPH_CONF_H */
258 
use alternate function 7
USART_TypeDef * dev
USART device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 6
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.