boards/nucleo-f401/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Lari Lehtomäki
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
32 /* 0: no external high speed crystal available
33  * else: actual crystal frequency [in Hz] */
34 #define CLOCK_HSE (8000000U)
35 /* 0: no external low speed crystal available,
36  * 1: external crystal available (always 32.768kHz) */
37 #define CLOCK_LSE (1)
38 /* give the target core clock (HCLK) frequency [in Hz],
39  * maximum: 84MHz */
40 #define CLOCK_CORECLOCK (84000000U)
41 /* PLL Output divisor */
42 #define P (4U)
43 /* peripheral clock setup */
44 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
45 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
46 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */
47 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
48 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */
49 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
50 
56 static const timer_conf_t timer_config[] = {
57  {
58  .dev = TIM5,
59  .max = 0xffffffff,
60  .rcc_mask = RCC_APB1ENR_TIM5EN,
61  .bus = APB1,
62  .irqn = TIM5_IRQn
63  }
64 };
65 
66 #define TIMER_0_ISR isr_tim5
67 
68 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
69 
75 static const uart_conf_t uart_config[] = {
76  {
77  .dev = USART2,
78  .rcc_mask = RCC_APB1ENR_USART2EN,
79  .rx_pin = GPIO_PIN(PORT_A, 3),
80  .tx_pin = GPIO_PIN(PORT_A, 2),
81  .rx_af = GPIO_AF7,
82  .tx_af = GPIO_AF7,
83  .bus = APB1,
84  .irqn = USART2_IRQn,
85 #ifdef UART_USE_DMA
86  .dma_stream = 6,
87  .dma_chan = 4
88 #endif
89  },
90  {
91  .dev = USART6,
92  .rcc_mask = RCC_APB2ENR_USART6EN,
93  .rx_pin = GPIO_PIN(PORT_A, 12),
94  .tx_pin = GPIO_PIN(PORT_A, 11),
95  .rx_af = GPIO_AF8,
96  .tx_af = GPIO_AF8,
97  .bus = APB2,
98  .irqn = USART6_IRQn,
99 #ifdef UART_USE_DMA
100  .dma_stream = 6,
101  .dma_chan = 4
102 #endif
103  }
104 };
105 
106 #define UART_0_ISR (isr_usart2)
107 #define UART_0_DMA_ISR (isr_dma1_stream6)
108 #define UART_1_ISR (isr_usart6)
109 #define UART_1_DMA_ISR (isr_dma1_stream6)
110 
111 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
112 
118 static const pwm_conf_t pwm_config[] = {
119  {
120  .dev = TIM2,
121  .rcc_mask = RCC_APB1ENR_TIM2EN,
122  .chan = { { .pin = GPIO_PIN(PORT_A, 15) , .cc_chan = 0 },
123  { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
124  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
125  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
126  .af = GPIO_AF1,
127  .bus = APB1
128  },
129  {
130  .dev = TIM3,
131  .rcc_mask = RCC_APB1ENR_TIM3EN,
132  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
133  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
134  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
135  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
136  .af = GPIO_AF2,
137  .bus = APB1
138  },
139 };
140 
141 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
142 
151 static const uint8_t spi_divtable[2][5] = {
152  { /* for APB1 @ 42000000Hz */
153  7, /* -> 164062Hz */
154  6, /* -> 328125Hz */
155  4, /* -> 1312500Hz */
156  2, /* -> 5250000Hz */
157  1 /* -> 10500000Hz */
158  },
159  { /* for APB2 @ 84000000Hz */
160  7, /* -> 328125Hz */
161  7, /* -> 328125Hz */
162  5, /* -> 1312500Hz */
163  3, /* -> 5250000Hz */
164  2 /* -> 10500000Hz */
165  }
166 };
167 
168 static const spi_conf_t spi_config[] = {
169  {
170  .dev = SPI1,
171  .mosi_pin = GPIO_PIN(PORT_A, 7),
172  .miso_pin = GPIO_PIN(PORT_A, 6),
173  .sclk_pin = GPIO_PIN(PORT_A, 5),
174  .cs_pin = GPIO_PIN(PORT_A, 4),
175  .af = GPIO_AF5,
176  .rccmask = RCC_APB2ENR_SPI1EN,
177  .apbbus = APB2
178  },
179  {
180  .dev = SPI2,
181  .mosi_pin = GPIO_PIN(PORT_B, 15),
182  .miso_pin = GPIO_PIN(PORT_B, 14),
183  .sclk_pin = GPIO_PIN(PORT_B, 13),
184  .cs_pin = GPIO_PIN(PORT_B, 12),
185  .af = GPIO_AF5,
186  .rccmask = RCC_APB1ENR_SPI2EN,
187  .apbbus = APB1
188  },
189  {
190  .dev = SPI3,
191  .mosi_pin = GPIO_PIN(PORT_C, 12),
192  .miso_pin = GPIO_PIN(PORT_C, 11),
193  .sclk_pin = GPIO_PIN(PORT_C, 10),
194  .cs_pin = GPIO_UNDEF,
195  .af = GPIO_AF6,
196  .rccmask = RCC_APB1ENR_SPI3EN,
197  .apbbus = APB1
198  }
199 };
200 
201 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
202 
209 #define I2C_NUMOF (1U)
210 #define I2C_0_EN 1
211 #define I2C_IRQ_PRIO 1
212 #define I2C_APBCLK (CLOCK_APB1)
213 
214 /* I2C 0 device configuration */
215 #define I2C_0_DEV I2C1
216 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
217 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
218 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
219 #define I2C_0_EVT_ISR isr_i2c1_ev
220 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
221 #define I2C_0_ERR_ISR isr_i2c1_er
222 /* I2C 0 pin configuration */
223 #define I2C_0_SCL_PORT GPIOB
224 #define I2C_0_SCL_PIN 8
225 #define I2C_0_SCL_AF 4
226 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
227 #define I2C_0_SDA_PORT GPIOB
228 #define I2C_0_SDA_PIN 9
229 #define I2C_0_SDA_AF 4
230 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
231 
243 #define ADC_NUMOF (6U)
244 #define ADC_CONFIG { \
245  {GPIO_PIN(PORT_A, 0), 0, 0}, \
246  {GPIO_PIN(PORT_A, 1), 0, 1}, \
247  {GPIO_PIN(PORT_A, 4), 0, 4}, \
248  {GPIO_PIN(PORT_B, 0), 0, 8}, \
249  {GPIO_PIN(PORT_C, 1), 0, 11}, \
250  {GPIO_PIN(PORT_C, 0), 0, 10}, \
251 }
252 
258 #define DAC_NUMOF (0)
259 
265 #define RTC_NUMOF (1)
266 
268 #ifdef __cplusplus
269 }
270 #endif
271 
272 #endif /* PERIPH_CONF_H */
273 
use alternate function 7
USART_TypeDef * dev
USART device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 6
use alternate function 1
PWM configuration structure.
LPC_CTxxBx_Type * dev
PWM device.
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define a custom GPIO_UNDEF value.
SPI configuration data structure.
cc2538_gptimer_t * dev
timer device
Timer configuration data.
use alternate function 2
cc2538_ssi_t * dev
SSI device.