boards/nucleo-f401/include/periph_conf.h
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1 /*
2  * Copyright (C) 2015 Lari Lehtomäki
3  *
4  * This file is subject to the terms and conditions of the GNU Lesser
5  * General Public License v2.1. See the file LICENSE in the top level
6  * directory for more details.
7  */
8 
19 #ifndef PERIPH_CONF_H
20 #define PERIPH_CONF_H
21 
22 #include "periph_cpu.h"
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
35 /* give the target core clock (HCLK) frequency [in Hz],
36  * maximum: 84MHz */
37 #define CLOCK_CORECLOCK (84000000U)
38 /* 0: no external high speed crystal available
39  * else: actual crystal frequency [in Hz] */
40 #define CLOCK_HSE (8000000U)
41 /* 0: no external low speed crystal available,
42  * 1: external crystal available (always 32.768kHz) */
43 #define CLOCK_LSE (1)
44 /* peripheral clock setup */
45 #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
46 #define CLOCK_AHB (CLOCK_CORECLOCK / 1)
47 #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 42MHz */
48 #define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
49 #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 84MHz */
50 #define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
51 
52 /* Main PLL factors */
53 #define CLOCK_PLL_M (4)
54 #define CLOCK_PLL_N (168)
55 #define CLOCK_PLL_P (4)
56 #define CLOCK_PLL_Q (7)
57 
63 static const timer_conf_t timer_config[] = {
64  {
65  .dev = TIM5,
66  .max = 0xffffffff,
67  .rcc_mask = RCC_APB1ENR_TIM5EN,
68  .bus = APB1,
69  .irqn = TIM5_IRQn
70  }
71 };
72 
73 #define TIMER_0_ISR isr_tim5
74 
75 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
76 
82 static const uart_conf_t uart_config[] = {
83  {
84  .dev = USART2,
85  .rcc_mask = RCC_APB1ENR_USART2EN,
86  .rx_pin = GPIO_PIN(PORT_A, 3),
87  .tx_pin = GPIO_PIN(PORT_A, 2),
88  .rx_af = GPIO_AF7,
89  .tx_af = GPIO_AF7,
90  .bus = APB1,
91  .irqn = USART2_IRQn,
92 #ifdef UART_USE_DMA
93  .dma_stream = 6,
94  .dma_chan = 4
95 #endif
96  },
97  {
98  .dev = USART6,
99  .rcc_mask = RCC_APB2ENR_USART6EN,
100  .rx_pin = GPIO_PIN(PORT_A, 12),
101  .tx_pin = GPIO_PIN(PORT_A, 11),
102  .rx_af = GPIO_AF8,
103  .tx_af = GPIO_AF8,
104  .bus = APB2,
105  .irqn = USART6_IRQn,
106 #ifdef UART_USE_DMA
107  .dma_stream = 6,
108  .dma_chan = 4
109 #endif
110  }
111 };
112 
113 #define UART_0_ISR (isr_usart2)
114 #define UART_0_DMA_ISR (isr_dma1_stream6)
115 #define UART_1_ISR (isr_usart6)
116 #define UART_1_DMA_ISR (isr_dma1_stream6)
117 
118 #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
119 
125 static const pwm_conf_t pwm_config[] = {
126  {
127  .dev = TIM2,
128  .rcc_mask = RCC_APB1ENR_TIM2EN,
129  .chan = { { .pin = GPIO_PIN(PORT_A, 15) , .cc_chan = 0 },
130  { .pin = GPIO_PIN(PORT_B, 3) /* D3 */, .cc_chan = 1 },
131  { .pin = GPIO_PIN(PORT_B, 10) /* D6 */, .cc_chan = 2 },
132  { .pin = GPIO_UNDEF, .cc_chan = 0 } },
133  .af = GPIO_AF1,
134  .bus = APB1
135  },
136  {
137  .dev = TIM3,
138  .rcc_mask = RCC_APB1ENR_TIM3EN,
139  .chan = { { .pin = GPIO_PIN(PORT_B, 4) /* D5 */, .cc_chan = 0 },
140  { .pin = GPIO_PIN(PORT_C, 7) /* D9 */, .cc_chan = 1 },
141  { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2 },
142  { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3 } },
143  .af = GPIO_AF2,
144  .bus = APB1
145  },
146 };
147 
148 #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
149 
158 static const uint8_t spi_divtable[2][5] = {
159  { /* for APB1 @ 42000000Hz */
160  7, /* -> 164062Hz */
161  6, /* -> 328125Hz */
162  4, /* -> 1312500Hz */
163  2, /* -> 5250000Hz */
164  1 /* -> 10500000Hz */
165  },
166  { /* for APB2 @ 84000000Hz */
167  7, /* -> 328125Hz */
168  7, /* -> 328125Hz */
169  5, /* -> 1312500Hz */
170  3, /* -> 5250000Hz */
171  2 /* -> 10500000Hz */
172  }
173 };
174 
175 static const spi_conf_t spi_config[] = {
176  {
177  .dev = SPI1,
178  .mosi_pin = GPIO_PIN(PORT_A, 7),
179  .miso_pin = GPIO_PIN(PORT_A, 6),
180  .sclk_pin = GPIO_PIN(PORT_A, 5),
181  .cs_pin = GPIO_PIN(PORT_A, 4),
182  .af = GPIO_AF5,
183  .rccmask = RCC_APB2ENR_SPI1EN,
184  .apbbus = APB2
185  },
186  {
187  .dev = SPI2,
188  .mosi_pin = GPIO_PIN(PORT_B, 15),
189  .miso_pin = GPIO_PIN(PORT_B, 14),
190  .sclk_pin = GPIO_PIN(PORT_B, 13),
191  .cs_pin = GPIO_PIN(PORT_B, 12),
192  .af = GPIO_AF5,
193  .rccmask = RCC_APB1ENR_SPI2EN,
194  .apbbus = APB1
195  },
196  {
197  .dev = SPI3,
198  .mosi_pin = GPIO_PIN(PORT_C, 12),
199  .miso_pin = GPIO_PIN(PORT_C, 11),
200  .sclk_pin = GPIO_PIN(PORT_C, 10),
201  .cs_pin = GPIO_UNDEF,
202  .af = GPIO_AF6,
203  .rccmask = RCC_APB1ENR_SPI3EN,
204  .apbbus = APB1
205  }
206 };
207 
208 #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
209 
216 #define I2C_NUMOF (1U)
217 #define I2C_0_EN 1
218 #define I2C_IRQ_PRIO 1
219 #define I2C_APBCLK (CLOCK_APB1)
220 
221 /* I2C 0 device configuration */
222 #define I2C_0_DEV I2C1
223 #define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
224 #define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
225 #define I2C_0_EVT_IRQ I2C1_EV_IRQn
226 #define I2C_0_EVT_ISR isr_i2c1_ev
227 #define I2C_0_ERR_IRQ I2C1_ER_IRQn
228 #define I2C_0_ERR_ISR isr_i2c1_er
229 /* I2C 0 pin configuration */
230 #define I2C_0_SCL_PORT GPIOB
231 #define I2C_0_SCL_PIN 8
232 #define I2C_0_SCL_AF 4
233 #define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
234 #define I2C_0_SDA_PORT GPIOB
235 #define I2C_0_SDA_PIN 9
236 #define I2C_0_SDA_AF 4
237 #define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
238 
250 #define ADC_NUMOF (6U)
251 #define ADC_CONFIG { \
252  {GPIO_PIN(PORT_A, 0), 0, 0}, \
253  {GPIO_PIN(PORT_A, 1), 0, 1}, \
254  {GPIO_PIN(PORT_A, 4), 0, 4}, \
255  {GPIO_PIN(PORT_B, 0), 0, 8}, \
256  {GPIO_PIN(PORT_C, 1), 0, 11}, \
257  {GPIO_PIN(PORT_C, 0), 0, 10}, \
258 }
259 
265 #define RTC_NUMOF (1)
266 
268 #ifdef __cplusplus
269 }
270 #endif
271 
272 #endif /* PERIPH_CONF_H */
273 
use alternate function 7
void * dev
UART, USART or LEUART device used.
TIMER_TypeDef * dev
TIMER device used.
use alternate function 8
#define GPIO_PIN(x, y)
Define a CPU specific GPIO pin generator macro.
use alternate function 6
use alternate function 1
PWM device configuration.
NRF_TIMER_Type * dev
timer device
use alternate function 5
UART device configuration.
#define GPIO_UNDEF
Define custom value to speficy undefined or unused GPIOs.
SPI module configuration options.
Timer configuration.
use alternate function 2
cc2538_ssi_t * dev
SSI device.